代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
www.eeworm.com/read/450842/7476020

vhd leon.vhd

---------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 1999 European Space Agency (ESA) -- -- This library
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vhd pci_gr.vhd

---------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) Gaisler Research 2003 -- -- This library is free soft
www.eeworm.com/read/450842/7476024

vhd leon_eth_pci.vhd

---------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 1999 European Space Agency (ESA) -- -- This library
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vhd ahbram.vhd

---------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 2003 Gaisler Research -- -- This library is free soft
www.eeworm.com/read/450211/7488483

vhd f1_zb.vhd

--------0度相位载波-------- library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity f1_zb is port (clk :in std_logic; dout :ou
www.eeworm.com/read/450211/7488495

vhd mux.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mux is port (q1,q2 :in std_logic_vector (7 downto 0); m :in std_logic;
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vhd f2_zb.vhd

--------0度相位载波-------- library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity f2_zb is port (clk :in std_logic; dout :ou
www.eeworm.com/read/449305/7509010

vhd testbench.vhd

library ieee; use STD.TEXTIO.all; use IEEE.STD_LOGIC_TEXTIO.all; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; use IEEE.std_logic_arith.all; entity testbench is end testbench;
www.eeworm.com/read/449246/7516385

vhd x95288xl.vhd

--Use X95288XL complete qlb4.0 logic; --author bozhang; --2007.04.20 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity x95288xl is port ( --
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vhd reg32.vhd

library ieee; use ieee.std_logic_1164.all; entity reg32 is port(load:in std_logic; datain:in std_logic_vector(31 downto 0); dataout:out std_logic_vector(31 downto 0)); end entity;