代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/469882/6928802
vhd 二進位3-bit補述產生器.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--D Flip-Flop
entity dff is
port(CLK, RESET, D : in std_logic;
Q :
www.eeworm.com/read/267307/6933128
vhd bus_51.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BUS_51 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT
www.eeworm.com/read/267307/6933162
vhd mul2_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_1 IS
PORT(X1,X2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK:IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX2_1;
ARCHITECTURE ART
www.eeworm.com/read/267307/6933165
vhd mux2_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_1 IS
PORT(X1,X2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL:IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX2_1;
ARCHITECTURE ART
www.eeworm.com/read/267307/6933167
vhd mux2e.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2E IS
PORT(
ADDRESR,ADDRESW: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
ADDRES: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
RDR,WRR,RDW,WRW:IN STD
www.eeworm.com/read/267307/6933180
vhd mux.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2E IS
PORT(
ADDRESR,ADDRESW: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
ADDRES: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
RDR,WRR,RDW,WRW:IN STD
www.eeworm.com/read/267307/6933188
vhd sram_adw.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY SRAM_ADW IS
PORT(
CLK,EN,SAVE: IN STD_LOGIC;
AIN: IN STD_LOGIC_VEC
www.eeworm.com/read/267307/6933200
vhd mux_trigger.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2E IS
PORT(
ADDRESR,ADDRESW: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
ADDRES: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
RDR,WRR,RDW,WRW:IN STD
www.eeworm.com/read/267307/6933423
vhd bus_51.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BUS_51 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT
www.eeworm.com/read/267307/6933451
vhd mul2_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_1 IS
PORT(X1,X2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK:IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX2_1;
ARCHITECTURE ART