mul2_1.vhd

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_1 IS
PORT(X1,X2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	 CLK:IN STD_LOGIC;
	 Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX2_1;
ARCHITECTURE ART OF MUX2_1 IS
SIGNAL SEL: STD_LOGIC;
BEGIN
	PROCESS(CLK)
	BEGIN
		IF CLK'EVENT AND CLK='0'THEN
            IF SEL='0' THEN
                Q<=X1;
	        ELSE Q<=X2;
	        END IF;
	        SEL<=NOT SEL;
		END IF;
	END PROCESS;
END ART;