代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/270913/11020622
vhd and2.vhd
library ieee;
use ieee.std_logic_1164.all;
entity andd is
port(x,y:in std_logic;
z:out std_logic_vector(1 downto 0));
end andd;
architecture andd of andd is
begin
z
www.eeworm.com/read/270913/11020667
vhd psk.vhd
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity PSK is
port(clk,enable:in std_logic;
x: in std_logic_vector(11 downto 0);
q:out std_logic_vector(1
www.eeworm.com/read/270913/11020702
vhd ask.vhd
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity ASK is
port(clk,enable:in std_logic;
x: in std_logic_vector(11 downto 0);
q:out std_logic_vector(1
www.eeworm.com/read/270913/11022944
vhd andd.vhd
library ieee;
use ieee.std_logic_1164.all;
entity andd is
port(x,y:in std_logic;
z:out std_logic_vector(1 downto 0));
end andd;
architecture andd of andd is
begin
z
www.eeworm.com/read/270524/11034286
vhd warming.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity warming is
port(clk: in std_logic;
finishc:in std_logic;
warn:out std_logic
);
end warming;
a
www.eeworm.com/read/270506/11034398
vhdl reg30b.vhdl
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG30B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
www.eeworm.com/read/416057/11043029
vhd abortgenerator.vhd
--****************************************************************************************************
-- Behavioural model of ABORT generation for ARM core simualtion
-- Designed by Ruslan Lepeteno
www.eeworm.com/read/416057/11043034
vhd armmultipliertesttop.vhd
--****************************************************************************************************
-- Multiplier tester top entity for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 27.01
www.eeworm.com/read/416057/11043035
vhd armcoresimtop.vhd
--****************************************************************************************************
-- Top entity for ARM Core simulation
-- Designed by Ruslan Lepetenok
-- Modified 04.02.2003
www.eeworm.com/read/416057/11043037
vhd armpackage.vhd
--****************************************************************************************************
-- Constants for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 30.01.2003
--**********