reg30b.vhdl

rom地址宽度8位

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG30B IS
   PORT (  Load : IN STD_LOGIC;
           DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
           DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
	END REG30B;

ARCHITECTURE behav OF REG30B IS
  BEGIN
   PROCESS(Load, DIN)
      BEGIN
  		IF Load'EVENT AND Load = '1' THEN  
		 DOUT <= DIN;   
		END IF;
  END PROCESS;
END behav;