count_key.vhd

来自「rom地址宽度8位」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY COUNT_KEY IS
 PORT (KEY: IN  STD_LOGIC;
   	   CLEAR:IN STD_LOGIC; 
	   FWORD_KEY : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	  );
END ;

ARCHITECTURE BEHA OF COUNT_KEY IS
SIGNAL Q:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
  PROCESS(KEY,CLEAR)
	BEGIN
      IF CLEAR='1'	 THEN
		Q<="00000000";
	   ELSIF KEY'EVENT and KEY='1'  THEN
		Q<=Q+1;	
		END IF;	
	END PROCESS; 	   
FWORD_KEY<=Q;
END BEHA;