andd.vhd

来自「fpga的应用」· VHDL 代码 · 共 11 行

library ieee;
use ieee.std_logic_1164.all;
entity andd is
  port(x,y:in std_logic;
       z:out std_logic_vector(1 downto 0));
end andd;
architecture andd of andd is
begin
    z<=x&y;
end andd;