ask.vhd

fpga的应用

library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity ASK is
   port(clk,enable:in std_logic;
		x: in std_logic_vector(11 downto 0);
        q:out std_logic_vector(11 downto 0));
end ASK;
architecture behav of ASK IS
begin
process(clk,enable)
  begin
    if clk='1' then
	  if enable='1' then 
	      q<=x;
	  end if;
	else q<="000000000000";
	end if;
end process;    
end behav;