代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
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txt 电梯.txt
一个VHDL电梯控制器的程序
1、 每层电梯的入口处设有上下请求开关，电梯内设有乘客到达层次的停站请求开关。
2、 设有电梯所处位置指示装置及电梯运行模式（上升或下降）指示装置。
3、 电梯每秒升降一层。
4、 电梯到达有停站请求的楼层后，经过1s电梯打开，开门只是灯亮，开门4s后，电梯门关闭（关门指示灯灭），电梯继续运行，直至执行完请求信号后停在 ...
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vhd test.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY test IS
PORT (
AD_RAM_LED1: OUT STD_LOGIC;
AD_RAM
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vhd tonetaba.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ToneTaba IS
PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CODE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ;
HIGH : OUT STD_LOGIC;
Tone : O
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vhd songer.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS
PORT ( CLK12MHZ : IN STD_LOGIC;
CLK8HZ : IN STD_LOGIC;
CODE1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
HIGH1 : OUT STD_LOGIC;
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vhd notetabs.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY NoteTabs IS
PORT ( clk : IN STD_LOGIC;
ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
END;
ARCHITECTURE
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vhd xxx.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:21:47 11/08/2006
-- Design Name: xccpld
-- Module Name: x
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vhd writefifo.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
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vhd i60bcd.vhd
--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity i60bcd i
www.eeworm.com/read/274276/10879322
vhd regne.vhd
--regne.vhd n-bit register with enable
library ieee ;
use ieee.std_logic_1164.all ;
entity regne is
generic ( n : integer := 12 ) ;
port (
r : in std_logic_vector(n-1 downto 0) ;--register
www.eeworm.com/read/274276/10879373
vhd negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块