xxx.vhd

通过PC104访问内存地址

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   15:21:47 11/08/2006
-- Design Name:   xccpld
-- Module Name:   xxx.vhd
-- Project Name:  xccpld
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: xccpld
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY xxx_vhd IS
END xxx_vhd;

ARCHITECTURE behavior OF xxx_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT xccpld
	PORT(
		A : IN std_logic_vector(19 downto 0);
		AEN : IN std_logic;
		IOW : IN std_logic;
		IOR : IN std_logic;
		RESET : IN std_logic;          
		CS1 : OUT std_logic;
		CS2 : OUT std_logic;
		OE : OUT std_logic;
		ALE : OUT std_logic;
		WR : OUT std_logic;
		RD : OUT std_logic;
		RST : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL AEN :  std_logic := '0';
	SIGNAL IOW :  std_logic := '0';
	SIGNAL IOR :  std_logic := '0';
	SIGNAL RESET :  std_logic := '0';
	SIGNAL A :  std_logic_vector(19 downto 0) := (others=>'0');

	--Outputs
	SIGNAL CS1 :  std_logic;
	SIGNAL CS2 :  std_logic;
	SIGNAL OE :  std_logic;
	SIGNAL ALE :  std_logic;
	SIGNAL WR :  std_logic;
	SIGNAL RD :  std_logic;
	SIGNAL RST :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: xccpld PORT MAP(
		A => A,
		AEN => AEN,
		IOW => IOW,
		IOR => IOR,
		RESET => RESET,
		CS1 => CS1,
		CS2 => CS2,
		OE => OE,
		ALE => ALE,
		WR => WR,
		RD => RD,
		RST => RST
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;