notetabs.vhd

用VHDL语言写的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY NoteTabs IS
	PORT ( clk : IN STD_LOGIC;
			ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
	END;
ARCHITECTURE one OF NoteTabs IS
COMPONENT MUSIC
 PORT (address : IN STD_LOGIC_VECTOR (7 DOWNTO 0 );
		inclock : IN STD_LOGIC;
		q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
 END COMPONENT;
	SIGNAL Counter : STD_LOGIC_VECTOR (7 DOWNTO 0);
 BEGIN
	CNT8 : PROCESS(clk, Counter)
	BEGIN
		IF Counter=138 THEN Counter <= "00000000";
		ELSIF (clk'EVENT AND clk = '1') THEN Counter <= Counter+1;END IF;
	END PROCESS;
u1 : MUSIC PORT MAP (address=>Counter , q=>ToneIndex, inclock=>clk);
END;