📄 writefifo.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity writefifo is
port(
s2 : in std_logic;
fosc : in std_logic;
glrn : in std_logic;
request : in std_logic;
ldsrqustin : in std_logic; --read mode
dclkin : in std_logic;
datain : in std_logic_vector(7 downto 0);
beiflag : in std_logic;
lvdsdtain : in std_logic_vector(7 downto 0);
lvdsflag : in std_logic;
lvdsrclk : in std_logic;
Lock : in std_logic;
usbchoose : in std_logic;
rws : in std_logic;
L6 : out std_logic;
L5 : out std_logic;
refclk : out std_logic;
rclk_rf : out std_logic;
tclk : out std_logic;
tclk_rf : out std_logic;
flashclk : out std_logic;
rwen : out std_logic;
beiflagout : out std_logic;
lvdsrwenout : out std_logic;
chooseout : out std_logic;
choose : out std_logic;
fifowr : out std_logic;
addwr : out std_logic_vector(11 downto 0);
oe245 : out std_logic;
lvdsrwen : out std_logic_vector(3 downto 0);
ldsrqustout : out std_logic_vector(3 downto 0);
dataout : out std_logic_vector(7 downto 0);
fifodo : out std_logic_vector(7 downto 0) --fifo data output
);
end writefifo;
architecture Behavioral of writefifo is
signal f_addwr : std_logic_vector(11 downto 0); --write address
signal f_data : std_logic_vector(7 downto 0);
type brq is (br0,br1,br2,br3,br4,br5,br6,br7,br8,br9,br10,br11,br12,br13,br14,br15,br16,br17,br18,br19,br20,br21,br22,br23,br24,br25,br26,br27,br28,br29,br30,br31,br32,br33,br34,br35,br36,br37,br38,br39,br40,br41,br42,br43,br44,br45,br46,br47,br48,br49,br50,br51,br52,br53);
signal b_state : brq;
signal wrclk : std_logic;
signal f_zcount : std_logic_vector(23 downto 0);
signal fdclkin : std_logic;
signal state : std_logic;
signal fenpclk : std_logic;
signal rwsoe : std_logic;
signal f_beiflag : std_logic;
signal f_s2 : std_logic;
signal f_rws : std_logic;
signal f_count : std_logic_vector(4 downto 0);
signal countlvds0 : std_logic_vector(3 downto 0);
signal countlvds1 : std_logic_vector(3 downto 0);
signal f_lvds0 : std_logic_vector(3 downto 0);
signal f_lvds1 : std_logic_vector(3 downto 0);
signal f_lvdsrwen : std_logic_vector(3 downto 0);
signal f_ldsrqustout : std_logic_vector(3 downto 0);
signal clkcount : std_logic_vector(1 downto 0);
signal f_rwcount : std_logic_vector(13 downto 0);
signal f_rbcount : std_logic_vector(1 downto 0);
signal lvf_addwr : std_logic_vector(11 downto 0);
signal f_command : std_logic_vector(6 downto 0);
signal f_beiflagwcount : std_logic_vector(19 downto 0);
signal f_s2wcount : std_logic_vector(19 downto 0);
begin
choose<= usbchoose;
flashclk <=wrclk;
rwen<=rws;
state<=rws;
ldsrqustout<=f_ldsrqustout;
lvdsrwen<=f_lvdsrwen;
oe245<=rwsoe;
rclk_rf<='1';
tclk_rf<='1';
refclk<=fenpclk;
tclk<=fenpclk;
beiflagout<=f_beiflag;
lvdsrwenout<=rws;
chooseout<=usbchoose;
L6<=Lock;
---------------------------------------------------
L5<=rws when(f_s2='1')
else '0' ;
-------------------------------
lds0: process(glrn,fenpclk)
begin
if glrn='0' then
countlvds0<="0000";
elsif fenpclk ' event and fenpclk='0' then
countlvds0<=countlvds0+1;
if countlvds0 >="0111" then
countlvds0<="0000";
end if;
f_lvds0<=countlvds0;
end if;
end process lds0;
lds1: process(glrn,fenpclk)
begin
if glrn='0' then
countlvds1<="1000";
elsif fenpclk ' event and fenpclk='0' then
countlvds1<=countlvds1+1;
if countlvds1="1111"or countlvds1<"1000" then
countlvds1<="1000";
end if;
f_lvds1<=countlvds1;
end if;
end process lds1;
f_ldsrqustout<=f_lvds0 when(ldsrqustin='0')
else f_lvds1;
f_lvdsrwen<=f_lvds0 when(rws='0' or f_s2='0')
else f_lvds1;
--------------------------
p3:process(glrn,fosc)
variable fcnt : std_logic_vector(7 downto 0);
begin
if glrn='0' then
wrclk<='1';
b_state<=br0;
elsif fosc'event and fosc='1' then
if state='1' then
case b_state is
when br0 =>
wrclk<='0';
b_state <= br1;
when br1 =>
dataout<=f_data ;
b_state <= br2;
when br2 =>
f_count<="00000";
b_state <= br3;
when br3=>
if f_count="11110" then
f_count<="00000";
b_state <= br4;
else
f_count<=f_count+1;
b_state<=br3;
end if;
when br4=>
b_state <= br5;
when br5 =>
wrclk<='1';
b_state <= br6;
when br6=>
f_count<="00000";
b_state <= br7;
when br7=>
if f_count="11110" then
f_count<="00000";
b_state <= br8;
else
f_count<=f_count+1;
b_state<=br7;
end if;
when br8=>
b_state<=br9;
when br9=>
f_count<="00000";
b_state<=br10;
when br10 =>
if fcnt = X"FB" then
f_data <= f_zcount(23 downto 16);
fcnt := X"FC";
elsif fcnt = X"FC" then
f_data <= f_zcount(15 downto 8);
fcnt := X"FD";
elsif fcnt = X"FD" then
f_data <= f_zcount(7 downto 0);
fcnt := X"FE";
elsif fcnt = X"FE" then
f_data <= X"EB";
fcnt := X"FF";
elsif fcnt=X"FF" then
f_data <= X"90";
fcnt := X"00";
f_zcount <= f_zcount + 1;
else
f_data <= fcnt;
fcnt := fcnt + 1;
end if;
b_state <= br0;
when others =>
b_state <= br0;
end case;
end if;
end if;
end process p3;
-------------------------------------------------
dclkin xiaodou
p4: process(glrn, fosc,dclkin)
begin
if glrn='0' then
f_rbcount<="00";
fdclkin<='1';
elsif fosc ' event and fosc='1' then
if dclkin='0' and f_rbcount(1)='0' and fdclkin='1' then
f_rbcount<=f_rbcount+1;
fdclkin<='1';
elsif dclkin='0' and f_rbcount(1)='1' and fdclkin='1' then
fdclkin<='0';
f_rbcount<="00";
elsif dclkin='1' and f_rbcount(1)='0' and fdclkin='0' then
fdclkin<='0';
f_rbcount<=f_rbcount+1;
elsif dclkin='1' and f_rbcount(1)='1' and fdclkin='0' then
fdclkin<='1';
f_rbcount<="00";
else
f_rbcount<="00";
end if;
end if;
end process p4;
--
---------------------------------------------------
p2: process(glrn,request,f_beiflag,fdclkin,datain,lvdsflag,lvdsdtain,f_addwr,lvf_addwr,lvdsrclk)
begin
if request='1' or glrn ='0'then --
f_addwr<="000000000000";
lvf_addwr<="000000000000";
elsif f_beiflag='0'then
addwr<=f_addwr;
fifowr<=fdclkin;
fifodo<=datain;
if fdclkin'event and fdclkin='0' then
f_addwr<=f_addwr+1;
end if;
else
addwr<=lvf_addwr;
fifowr<= lvdsrclk;
if lvdsflag='0'then
if lvdsrclk'event and lvdsrclk='0' then
lvf_addwr<=lvf_addwr+1;
fifodo<=lvdsdtain;
end if;
end if;
end if;
end process p2;
----------------------------------------------------
when (flag='0')
p5: process(glrn, fosc)
begin
if glrn='0' then
f_rwcount<="00000000000000";
rwsoe<='0';
elsif fosc ' event and fosc='1' then
if rws='0' and f_rwcount(13)='0' and rwsoe='1' then
f_rwcount<=f_rwcount+1;
rwsoe<='1';
elsif rws='0' and f_rwcount(13)='1' and rwsoe='1' then
rwsoe<='0';
f_rwcount<="00000000000000";
elsif rws='1' and f_rwcount(12)='0' and rwsoe='0' then
rwsoe<='0';
f_rwcount<=f_rwcount+1;
elsif rws='1' and f_rwcount(12)='1' and rwsoe='0' then
rwsoe<='1';
f_rwcount<="00000000000000";
else
f_rwcount<="00000000000000";
end if;
end if;
end process p5;
--------------------------------------------------
p6: process(glrn, fosc)
begin
if glrn='0' then
f_beiflagwcount<=X"00000";
f_beiflag<='0';
elsif fosc ' event and fosc='1' then
if beiflag='0' and f_beiflagwcount(19)='0' and f_beiflag='1' then
f_beiflagwcount<=f_beiflagwcount+1;
f_beiflag<='1';
elsif beiflag='0' and f_beiflagwcount(19)='1' and f_beiflag='1' then
f_beiflag<='0';
f_beiflagwcount<=X"00000";
elsif beiflag='1' and f_beiflagwcount(19)='0' and f_beiflag='0' then
f_beiflag<='0';
f_beiflagwcount<=f_beiflagwcount+1;
elsif beiflag='1' and f_beiflagwcount(19)='1' and f_beiflag='0' then
f_beiflag<='1';
f_beiflagwcount<=X"00000";
elsif beiflag='0' and f_beiflag='0' then
f_beiflag<='0';
f_beiflagwcount<=X"00000";
elsif beiflag='1' and f_beiflag='1' then
f_beiflag<='1';
f_beiflagwcount<=X"00000";
else
f_beiflagwcount<=X"00000";
end if;
end if;
end process p6;
----------------fen ping 产生命令的 无效位---------------
p8: process(glrn, fosc,clkcount)
begin
fenpclk<=clkcount(1);
if glrn='0' then
clkcount<="00";
elsif fosc ' event and fosc='1' then
clkcount<=clkcount+1;
end if;
end process p8;
-------------------------------------------------------------
p9: process(glrn, fenpclk)
begin
if glrn='0' then
f_command<="0000000";
elsif fenpclk ' event and fenpclk='0' then
f_command<=f_command+1;
end if;
end process p9;
p11: process(glrn, fosc)
begin
if glrn='0' then
f_s2wcount<=X"00000";
f_s2<='0';
elsif fosc ' event and fosc='1' then
if s2='0' and f_s2wcount(19)='0' and f_s2='1' then
f_s2wcount<=f_s2wcount+1;
f_s2<='1';
elsif s2='0' and f_s2wcount(19)='1' and f_s2='1' then
f_s2<='0';
f_s2wcount<=X"00000";
elsif beiflag='1' and f_s2wcount(19)='0' and f_s2='0' then
f_s2<='0';
f_s2wcount<=f_s2wcount+1;
elsif beiflag='1' and f_s2wcount(19)='1' and f_s2='0' then
f_s2<='1';
f_s2wcount<=X"00000";
elsif beiflag='0' and f_s2='0' then
f_s2<='0';
f_s2wcount<=X"00000";
elsif beiflag='1' and f_s2='1' then
f_s2<='1';
f_s2wcount<=X"00000";
else
f_s2wcount<=X"00000";
end if;
end if;
end process p11;
end Behavioral;
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