代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/351302/10660089
vhd cic_v6_1.vhd
-- megafunction wizard: %CIC v6.1%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- cic_v6_1_cic
-- ============================
www.eeworm.com/read/351302/10660132
vhd cic_v6_1.vhd
-- megafunction wizard: %CIC v6.1%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- cic_v6_1_cic
-- ============================
www.eeworm.com/read/422084/10665009
vhd jia.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity jia is
port( clk,a : in std_logic;
int : in std_logic_vector(3
www.eeworm.com/read/159079/10697328
vhd control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
www.eeworm.com/read/158953/10708997
vhd fenpin16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Fenpin16 is
port(a,b:in std_logic;
clk6:in std_logic;
clock6:out std_logic);
end;
archi
www.eeworm.com/read/350770/10712511
vhd dumb_targ32.vhd
--------------------------------------------------------------------------
--
-- File: dumb_targ32.vhd
-- Rev: 3.0.0
--
-- This is a functional simulation model for a simple target. This
--
www.eeworm.com/read/158843/10724394
mgf 1cordic_beh.mgf
I 000044 55 1915 1144462001000 rtl
(_unit VHDL (cordic_add 0 14 (rtl 0 29 ))
(_version v33)
(_time 1144462001000 2006.04.08 10:06:41)
(_source (\g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_
www.eeworm.com/read/421594/10727496
bak dds_vhdl.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC; --系统时钟
FWOR
www.eeworm.com/read/421594/10727560
vhd reg32b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO
www.eeworm.com/read/421594/10727651
vhd dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC; --系统时钟
FWOR