fenpin16.vhd

来自「在本示例程序中」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Fenpin16 is
    port(a,b:in std_logic;
         clk6:in std_logic;
         clock6:out std_logic);
end;
architecture one of Fenpin16 is
signal tmp:std_logic_vector(3 downto 0);
signal ddt:std_logic_vector(1 downto 0);
begin
process(clk6)
begin
if clk6'event and clk6='1' then
      tmp<=tmp+1;
end if;
ddt<=a&b;
case ddt is
when "00" => clock6<=tmp(3);
when "01" => clock6<=tmp(2);
when "10" => clock6<=tmp(1);
when "11" => clock6<=tmp(0);
when others =>null;
end case;
end process;
end;