dumb_targ32.vhd

xilinx官方PCIcore 有详细说明文档

--------------------------------------------------------------------------
--
--  File:   dumb_targ32.vhd
--  Rev:    3.0.0
--
--  This is a functional simulation model for a simple target.  This
--  is not synthesizable.  This file is only for simulation.
--
--  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
--
--------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity dumb_target32 is
  port (
        AD              : inout std_logic_vector(31 downto 0);
        CBE             : inout std_logic_vector( 3 downto 0);
        PAR             : inout std_logic;
        FRAME_N         : inout std_logic;
        TRDY_N          : inout std_logic;
        IRDY_N          : inout std_logic;
        STOP_N          : inout std_logic;
        DEVSEL_N        : inout std_logic;
        RST_N           : in    std_logic;
        CLK             : in    std_logic
  );
end dumb_target32;


architecture behave_arch of dumb_target32 is

  type ram_buffer32 is array (0 to 31) of std_logic_vector(31 downto 0);
  constant TDEL : time :=  5 ns;

  signal reg_ad         : std_logic_vector(31 downto 0);
  signal reg_cbe        : std_logic_vector( 3 downto 0);
  signal ad_oe          : std_logic := '0';
  signal cbe_oe         : std_logic := '0';
  signal reg_par        : std_logic := '1';
  signal par_oe         : std_logic := '0';
  signal reg_frame_n    : std_logic := '1';
  signal frame_oe       : std_logic := '0';
  signal reg_irdy_n     : std_logic := '1';
  signal irdy_oe        : std_logic := '0';
  signal reg_trdy_n     : std_logic := '1';
  signal trdy_oe        : std_logic := '0';
  signal reg_stop_n     : std_logic := '1';
  signal stop_oe        : std_logic := '0';
  signal reg_devsel_n   : std_logic := '1';
  signal devsel_oe      : std_logic := '0';
  signal valid_read     : std_logic := '0';
  signal valid_write    : std_logic := '0';
  signal cmd_mem        : ram_buffer32;


begin


  -- Define port hookup

  AD       <= reg_ad after TDEL when ad_oe='1' else (others=>'Z') after TDEL;
  CBE      <= reg_cbe after TDEL when cbe_oe='1' else (others=>'Z') after TDEL;
  PAR      <= reg_par after TDEL when par_oe='1' else 'Z' after TDEL;
  FRAME_N  <= reg_frame_n after TDEL when frame_oe='1' else 'Z' after TDEL;
  IRDY_N   <= reg_irdy_n after TDEL when irdy_oe='1' else 'Z' after TDEL;
  TRDY_N   <= reg_trdy_n after TDEL when trdy_oe='1' else 'Z' after TDEL;
  STOP_N   <= reg_stop_n after TDEL when stop_oe='1' else 'Z' after TDEL;
  DEVSEL_N <= reg_devsel_n after TDEL when devsel_oe='1' else 'Z' after TDEL;


  -- PCI Parity Generation

  process(CLK)
  begin
    if (CLK'event and CLK='1') then
      reg_par <= CBE(0) xor CBE(1) xor CBE(2) xor CBE(3) xor
                 AD( 0) xor AD( 1) xor AD( 2) xor AD( 3) xor
                 AD( 4) xor AD( 5) xor AD( 6) xor AD( 7) xor
                 AD( 8) xor AD( 9) xor AD(10) xor AD(11) xor
                 AD(12) xor AD(13) xor AD(14) xor AD(15) xor
                 AD(16) xor AD(17) xor AD(18) xor AD(19) xor
                 AD(20) xor AD(21) xor AD(22) xor AD(23) xor
                 AD(24) xor AD(25) xor AD(26) xor AD(27) xor
                 AD(28) xor AD(29) xor AD(30) xor AD(31)
                 after TDEL;
      par_oe <= ad_oe after TDEL;
    end if;
  end process;


  -- The actual target stuff begins here
 
  valid_read  <= '1' after TDEL
                     when (CBE="0110" or CBE="1100" or CBE="1110") else
                 '0' after TDEL;
  valid_write <= '1' after TDEL
                     when (CBE="0111") else
                 '0' after TDEL;


  process
    variable counter     : integer;
    variable cmd_read    : std_logic;
    variable cmd_write   : std_logic;
    variable old_frame_n : std_logic;

    -- Convert std_logic_vector to integer 
    function STD_TO_INT(in_val : in std_logic_vector) return integer is
      variable result  : integer := 0;
      variable failure : boolean := false;
    begin
      for i in in_val'range loop
        result := result * 2;
        case in_val(i) is
          when '0' => result := result + 0;
          when 'L' => result := result + 0;
          when '1' => result := result + 1;
          when 'H' => result := result + 1;
          when others => failure := true;
        end case;
      end loop;
      if failure then
        assert false report "STD_TO_INT error" severity warning;
      end if;
      return result;
    end STD_TO_INT;

    -- Procedure to act as normal target
    procedure NORMAL is
    begin
      if (old_frame_n = '1' and FRAME_N = '0' and
        (valid_read = '1' or valid_write = '1') and
        (AD(31 downto 16) = to_stdlogicvector(X"4000"))) then

        old_frame_n := '0';
        devsel_oe <= '1';
        stop_oe <= '1';
        trdy_oe <= '1';
        cmd_write := valid_write;
        cmd_read := valid_read;
        counter := STD_TO_INT("00" & AD(6 downto 2));
        reg_ad <= cmd_mem(counter);

        if valid_write= '1' then
          reg_devsel_n <= '0';
          reg_stop_n <= '1';
          reg_trdy_n <= '0';
        else
          reg_devsel_n <= '0';
          wait until CLK'event and CLK = '1';
          reg_stop_n <= '1';
          reg_trdy_n <= '0';
          ad_oe <= '1';
        end if;

        while old_frame_n = '0' loop
          wait until CLK'event and CLK = '1';
          while IRDY_N = '1' loop
            wait until CLK'event and CLK = '1';
          end loop;
          old_frame_n := FRAME_N;
          if cmd_write = '1' then
            cmd_mem(counter) <= AD;
          end if;
          if counter = 31 then counter := 0;
          else counter := counter + 1;
          end if;
          reg_ad <= cmd_mem(counter);
        end loop;

        ad_oe <= '0';
        reg_devsel_n <= '1';
        reg_stop_n <= '1';
        reg_trdy_n <= '1';
        wait until CLK'event and CLK = '1';
        devsel_oe <= '0';
        stop_oe <= '0';
        trdy_oe <= '0';
        old_frame_n := '1';
      end if;
    end NORMAL;


begin

  wait on RST_N, CLK;
  if (RST_N'event and RST_N = '1') then
    for loop_var in 0 to 31 loop
      cmd_mem(loop_var) <= conv_std_logic_vector(loop_var, 8)
      & "0000000000000000" & conv_std_logic_vector(loop_var, 8);
    end loop;
    reg_ad <= to_stdlogicvector(X"00000000");
    ad_oe <= '0';
    reg_cbe <= "0000";
    cbe_oe <= '0';
    reg_frame_n <= '1';
    frame_oe <= '0';
    reg_irdy_n <= '1';
    irdy_oe <= '0';
    reg_trdy_n <= '1';
    trdy_oe <= '0';
    reg_stop_n <= '1';
    stop_oe <= '0';
    reg_devsel_n <= '1';
    devsel_oe <= '0';
    old_frame_n := '1';
  elsif (CLK'event and CLK = '1' and RST_N = '1') then NORMAL;
  end if;

end process;


end behave_arch;