1cordic_beh.mgf

这是实现cordic算法的一些源程序

I 000044 55 1915          1144462001000 rtl
(_unit VHDL (cordic_add 0 14 (rtl 0 29 ))
  (_version v33)
  (_time 1144462001000 2006.04.08 10:06:41)
  (_source (\g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/cordic_add_rtl.vhd\))
  (_use (std(standard))(ieee(std_logic_unsigned))(ieee(std_logic_1164)))
  (_parameters dbg )
  (_entity
    (_time 1144462000922)
    (_use )
  )
  (_object
    (_port (_internal a ~extieee.std_logic_1164.std_logic 0 16 (_entity (_in ))))
    (_port (_internal b ~extieee.std_logic_1164.std_logic 0 17 (_entity (_in ))))
    (_type (_internal ~std_logic_vector{1~downto~0}~12 0 18 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 1)(i 0))))))
    (_port (_internal op ~std_logic_vector{1~downto~0}~12 0 18 (_entity (_in ))))
    (_port (_internal sum ~extieee.std_logic_1164.std_logic 0 19 (_entity (_out ))))
    (_port (_internal clk ~extieee.std_logic_1164.std_logic 0 20 (_entity (_in )(_active)(_lastactive)(_event)(_lastevent)(_edge))))
    (_signal (_internal carry ~extieee.std_logic_1164.std_logic 0 30 (_architecture (_uni ))))
    (_type (_internal ~std_logic_vector{1~downto~0}~13 0 33 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 1)(i 0))))))
    (_variable (_internal result ~std_logic_vector{1~downto~0}~13 0 33 (_process 0 )))
    (_process
      (main_prc(_architecture 0 0 32 (_process (_simple)(_target(5)(3))(_sensitivity(4))(_read(5)(2)(1)(0)))))
    )
    (_subprogram
      (_external resolved (ieee std_logic_1164 0))
    )
    (_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
    (_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
    (_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
  )
  (_static
    (3 3 )
    (3 2 )
    (2 3 )
    (2 2 )
    (2 2 )
  )
  (_model . rtl 1 -1
  )
)
I 000044 55 9720          1144462001313 beh
(_unit VHDL (cordic_control 0 14 (beh 0 57 ))
  (_version v33)
  (_time 1144462001312 2006.04.08 10:06:41)
  (_source (\g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/cordic_control_rtl.vhd\))
  (_use (std(standard))(ieee(numeric_std))(ieee(std_logic_1164)))
  (_parameters dbg )
  (_entity
    (_time 1144462001266)
    (_use )
  )
  (_object
    (_port (_internal clk ~extieee.std_logic_1164.std_logic 0 16 (_entity (_in )(_active)(_lastactive)(_event)(_lastevent)(_edge))))
    (_port (_internal enable ~extieee.std_logic_1164.std_logic 0 17 (_entity (_in ))))
    (_port (_internal reset ~extieee.std_logic_1164.std_logic 0 18 (_entity (_in ))))
    (_type (_internal ~std_logic_vector{15~downto~0}~12 0 19 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_port (_internal theta ~std_logic_vector{15~downto~0}~12 0 19 (_entity (_in ))))
    (_port (_internal x_data1 ~extieee.std_logic_1164.std_logic 0 20 (_entity (_in ))))
    (_port (_internal x_value ~extieee.std_logic_1164.std_logic 0 21 (_entity (_in ))))
    (_port (_internal y_data1 ~extieee.std_logic_1164.std_logic 0 22 (_entity (_in ))))
    (_port (_internal y_value ~extieee.std_logic_1164.std_logic 0 23 (_entity (_in ))))
    (_port (_internal z_value ~extieee.std_logic_1164.std_logic 0 24 (_entity (_in ))))
    (_port (_internal valid ~extieee.std_logic_1164.std_logic 0 25 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{15~downto~0}~122 0 26 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_port (_internal value ~std_logic_vector{15~downto~0}~122 0 26 (_entity (_out ))))
    (_port (_internal x_addend ~extieee.std_logic_1164.std_logic 0 27 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{3~downto~0}~12 0 28 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_port (_internal x_addr0 ~std_logic_vector{3~downto~0}~12 0 28 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{3~downto~0}~124 0 29 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_port (_internal x_addr1 ~std_logic_vector{3~downto~0}~124 0 29 (_entity (_out ))))
    (_port (_internal x_data0 ~extieee.std_logic_1164.std_logic 0 30 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{1~downto~0}~12 0 31 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 1)(i 0))))))
    (_port (_internal x_op ~std_logic_vector{1~downto~0}~12 0 31 (_entity (_out ))))
    (_port (_internal x_re0 ~extieee.std_logic_1164.std_logic 0 32 (_entity (_out ))))
    (_port (_internal x_re1 ~extieee.std_logic_1164.std_logic 0 33 (_entity (_out ))))
    (_port (_internal x_we0 ~extieee.std_logic_1164.std_logic 0 34 (_entity (_out ))))
    (_port (_internal y_addend ~extieee.std_logic_1164.std_logic 0 35 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{3~downto~0}~126 0 36 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_port (_internal y_addr0 ~std_logic_vector{3~downto~0}~126 0 36 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{3~downto~0}~128 0 37 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_port (_internal y_addr1 ~std_logic_vector{3~downto~0}~128 0 37 (_entity (_out ))))
    (_port (_internal y_data0 ~extieee.std_logic_1164.std_logic 0 38 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{1~downto~0}~1210 0 39 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 1)(i 0))))))
    (_port (_internal y_op ~std_logic_vector{1~downto~0}~1210 0 39 (_entity (_out ))))
    (_port (_internal y_re0 ~extieee.std_logic_1164.std_logic 0 40 (_entity (_out ))))
    (_port (_internal y_re1 ~extieee.std_logic_1164.std_logic 0 41 (_entity (_out ))))
    (_port (_internal y_we0 ~extieee.std_logic_1164.std_logic 0 42 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{3~downto~0}~1212 0 43 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_port (_internal z_addr0 ~std_logic_vector{3~downto~0}~1212 0 43 (_entity (_out ))))
    (_port (_internal z_data0 ~extieee.std_logic_1164.std_logic 0 44 (_entity (_out ))))
    (_port (_internal z_data1 ~extieee.std_logic_1164.std_logic 0 45 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{1~downto~0}~1214 0 46 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 1)(i 0))))))
    (_port (_internal z_op ~std_logic_vector{1~downto~0}~1214 0 46 (_entity (_out ))))
    (_port (_internal z_re0 ~extieee.std_logic_1164.std_logic 0 47 (_entity (_out ))))
    (_port (_internal z_romdata ~extieee.std_logic_1164.std_logic 0 48 (_entity (_out ))))
    (_port (_internal z_we0 ~extieee.std_logic_1164.std_logic 0 49 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{15~downto~0}~13 0 59 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_signal (_internal theta_shift_reg ~std_logic_vector{15~downto~0}~13 0 59 (_architecture (_uni ))))
    (_signal (_internal value_shift_reg ~std_logic_vector{15~downto~0}~13 0 59 (_architecture (_uni ))))
    (_signal (_internal zsign ~extieee.std_logic_1164.std_logic 0 60 (_architecture (_uni ))))
    (_signal (_internal clear_addend ~extieee.std_logic_1164.std_logic 0 61 (_architecture (_uni ))))
    (_type (_internal ~std_logic_vector{15~downto~0}~1316 0 62 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_constant (_internal initx ~std_logic_vector{15~downto~0}~1316 0 62 (_architecture (_string \"0100110110111010"\))))
    (_type (_internal romword 0 63 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_type (_internal ~std_logic_vector{15~downto~0}~1319 0 64 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_type (_internal rom 0 64 (_array ~std_logic_vector{15~downto~0}~1319 ((_to (i 0)(i 11))))))
    (_constant (_internal zrom rom 0 65 (_architecture ((((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2)))(((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2)))(((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 3))((i 3))((i 3))((i 3))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 3)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2)))))))
    (_type (_internal ~std_logic_vector{15{15~downto~1}~13 0 191 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 1))))))
    (_type (_internal ~std_logic_vector{15{15~downto~1}~1323 0 241 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 1))))))
    (_type (_internal ~std_logic_vector{15{15~downto~1}~1324 0 245 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 1))))))
    (_process
      (main_prc(_architecture 0 0 80 (_process (_target(20)(32)(31)(30)(12)(9)(28)(27)(33)(26)(25)(24)(23)(14)(13)(18)(17)(16)(15)(22)(21)(34)(35)(36)(37)))))
      (line__265(_architecture 1 0 265 (_assignment (_simple)(_alias((value)(value_shift_reg)))(_target(10))(_sensitivity(35)))))
      (line__266(_architecture 2 0 266 (_assignment (_simple)(_target(11))(_sensitivity(6)(37)))))
      (line__267(_architecture 3 0 267 (_assignment (_simple)(_target(19))(_sensitivity(4)(37)))))
    )
    (_subprogram
      (_internal write_ramx 4 0 82 (_architecture (_procedure )))
      (_internal write_ramy 5 0 92 (_architecture (_procedure )))
      (_internal write_ramz 6 0 102 (_architecture (_procedure )))
      (_internal read_ramx 7 0 112 (_architecture (_procedure )))
      (_internal read_ramy 8 0 122 (_architecture (_procedure )))
      (_internal read_ramz 9 0 132 (_architecture (_procedure )))
      (_internal default_all 10 0 139 (_architecture (_procedure )))
      (_internal start_cordic 11 0 171 (_architecture (_procedure )))
      (_internal load_theta 12 0 175 (_architecture (_procedure )))
      (_internal calculate 13 0 196 (_architecture (_procedure )))
      (_internal load_result 14 0 236 (_architecture (_procedure )))
      (_external resolved (ieee std_logic_1164 0))
    )
    (_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
    (_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
    (_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
    (_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))
    (_type (_external ~extSTD.STANDARD.NATURAL (std STANDARD NATURAL)))
  )
  (_static
    (2 2 2 2 )
    (2 2 2 2 )
    (2 2 )
    (2 2 2 2 )
    (2 2 2 2 )
    (2 2 )
    (2 2 2 2 )
    (2 2 )
    (2 3 )
    (2 3 )
    (2 3 )
  )
  (_model . beh 15 -1
  )
)
I 000044 55 2604          1144462001485 beh
(_unit VHDL (cordic_dpram 0 14 (beh 0 33 ))
  (_version v33)
  (_time 1144462001484 2006.04.08 10:06:41)
  (_source (\g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/cordic_dpram_beh.vhd\))
  (_use (std(standard))(ieee(numeric_std))(ieee(std_logic_1164)))
  (_parameters dbg )
  (_entity
    (_time 1144462001469)
    (_use )
  )
  (_object
    (_type (_internal ~std_logic_vector{3~downto~0}~12 0 16 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_port (_internal addr0 ~std_logic_vector{3~downto~0}~12 0 16 (_entity (_in ))))
    (_type (_internal ~std_logic_vector{3~downto~0}~122 0 17 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_port (_internal addr1 ~std_logic_vector{3~downto~0}~122 0 17 (_entity (_in ))))
    (_port (_internal clk ~extieee.std_logic_1164.std_logic 0 18 (_entity (_in )(_active)(_lastactive)(_event)(_lastevent)(_edge))))
    (_port (_internal re0 ~extieee.std_logic_1164.std_logic 0 19 (_entity (_in ))))
    (_port (_internal re1 ~extieee.std_logic_1164.std_logic 0 20 (_entity (_in ))))