代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/351933/10591361
vhd cic_v7_2.vhd
-- megafunction wizard: %CIC v7.2%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- cic_v7_2_cic
-- ============================
www.eeworm.com/read/351933/10591397
vhd cic_v7_2.vhd
-- megafunction wizard: %CIC v7.2%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- cic_v7_2_cic
-- ============================
www.eeworm.com/read/277838/10601220
vhd ﾣë.vhd
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Co
www.eeworm.com/read/277836/10601971
vhd pn.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:36:59 03/29/07
-- Design Name:
-- Module Name: pn - B
www.eeworm.com/read/422827/10607524
vhd counter.vhd
-- en,clr,接SW1,SW2
-- clk PIN28,(将IO_CLK与IO3相连,调节EDA_VI右边的拨码SW17--SW20,使输出1Hz时钟)
-- Q IO9--IO12 ,co IO13
-- VGA 4位功能选择位
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
www.eeworm.com/read/159535/10642668
vhd pipemult.vhd
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and
www.eeworm.com/read/422277/10650515
vhd count.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity count is
port(clk_1:in std_logic; --1HZ输入
sw:in std_logic; --状态判断输入
player1,player2:in
www.eeworm.com/read/351426/10652379
bak count.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count is
port(clk,clr,en:in std_logic;
q: out std_logic_vector (3
www.eeworm.com/read/351426/10652442
vhd count.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count is
port(clk,clr,en:in std_logic;
q: out std_logic_vector (3
www.eeworm.com/read/351426/10652479
bak vhdl1.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count is
port(clk,clr,en:in std_logic;
q: out std_logic_vector (3