count.vhd.bak

是vhdl语言

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity count is

port(clk,clr,en:in std_logic;
     
     q: out std_logic_vector (3 downto 0);
     full: out std_logic
);
end count;

architecture count_arc of count is
signal count_4: std_logic_vector (3 downto 0);
begin
q(0)<=count_4(0);
q(1)<=count_4(1);
q(2)<=count_4(2);
q(3)<=count_4(3);
process(clk,clr)
begin
  if(clr='0') then
     count_4<="0000";
  elsif (clk 'event and clk='1' and en='1') then
  --   if () then
       if (count_4="1001") then
         full<='1';
         count_4<="0000";
       else
         count_4<=count_4+'1';
         full<='0';
       end if;
     end if;
 --  end if;
end process;
end count_arc;