pipemult.vhd

使用Quartus II 5.0开发指导手册

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY pipemult IS 
	port
	(
		wren :  IN  STD_LOGIC;
		clk1 :  IN  STD_LOGIC;
		dataa :  IN  STD_LOGIC_VECTOR(7 downto 0);
		datab :  IN  STD_LOGIC_VECTOR(7 downto 0);
		rdaddress :  IN  STD_LOGIC_VECTOR(4 downto 0);
		wraddress :  IN  STD_LOGIC_VECTOR(4 downto 0);
		q :  OUT  STD_LOGIC_VECTOR(15 downto 0)
	);
END pipemult;

ARCHITECTURE bdf_type OF pipemult IS 

component mult
	PORT(clock : IN STD_LOGIC;
		 dataa : IN STD_LOGIC_VECTOR(7 downto 0);
		 datab : IN STD_LOGIC_VECTOR(7 downto 0);
		 result : OUT STD_LOGIC_VECTOR(15 downto 0)
	);
end component;

component ram
	PORT(clock : IN STD_LOGIC;
		 wren : IN STD_LOGIC;
		 data : IN STD_LOGIC_VECTOR(15 downto 0);
		 rdaddress : IN STD_LOGIC_VECTOR(4 downto 0);
		 wraddress : IN STD_LOGIC_VECTOR(4 downto 0);
		 q : OUT STD_LOGIC_VECTOR(15 downto 0)
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(15 downto 0);


BEGIN 



b2v_inst : mult
PORT MAP(clock => clk1,
		 dataa => dataa,
		 datab => datab,
		 result => SYNTHESIZED_WIRE_0);

b2v_inst1 : ram
PORT MAP(clock => clk1,
		 wren => wren,
		 data => SYNTHESIZED_WIRE_0,
		 rdaddress => rdaddress,
		 wraddress => wraddress,
		 q => q);

END;