代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/353516/10442764
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/279117/10462514
vhd ledy.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ledy is
port(clkin:in std_logic;
rst:in std_logic;
q:out std_logic_vector(0 to 7));
end ledy;
architecture behave of ledy is
begin
pro
www.eeworm.com/read/424113/10491724
vhd reg10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO
www.eeworm.com/read/352859/10498289
vhd picoblaze_amp_adc_control.vhd
--
-- KCPSM3 reference design - PicoBlaze controlling the two channel programmable
-- amplifier type LTC6912-1 and two channel A/D converter type LTC1407A-1 from
-- Linear Technology.
--
-- Des
www.eeworm.com/read/160647/10510867
txt program.txt
liberary ieee;
use ieee.std_logic_1164.all;
entity contraler is
port( clock:in std_logic;
light1,light2,light3,pause:out std_logic;
contral:out std_logic;
pause:in std_logic;
run,start
www.eeworm.com/read/423848/10529682
tdf fulladder.tdf
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is port(
a1,a2,c1: in std_logic;
c2,b: out std_logic);
end adder;
architecture behav of fulladder is
begin
b
www.eeworm.com/read/160403/10535234
vhi lms.vhi
-- VHDL Instantiation Created from source file lms.vhd -- 20:16:08 07/03/2005
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_lo
www.eeworm.com/read/160403/10535284
vhd test2.vhd
-- VHDL Test Bench Created from source file lms.vhd -- 20:25:36 07/03/2005
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the
www.eeworm.com/read/160403/10535298
tpl core.tpl
[COREGEN.VERILOG Component Instantiation.cosfunc]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change th
www.eeworm.com/read/278441/10535765
vhd testsuite.vhd
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- The Free IP Project
-- VHDL Free-DAC C