fulladder.tdf

使用Vhdl语言实现数字电路全加器功能

library ieee;
use ieee.std_logic_1164.all;
entity fulladder is port(
a1,a2,c1: in std_logic;
c2,b: out std_logic);
end adder;
architecture behav of fulladder is 
begin
b<=a1 xor a2 xor c1;
c2<=(a1 and a2)or(a1 and c1)or(a2 and c1);
end behav; 
package myadder is 
 component fulladder port(
 a1,a2,c1: in std_logic;
 c2,b: out std_logic);
 end component;
end myadder;
entity adder is port(
input1,input2: in std_logic_vector(0 to 3);
carryer: out std_logic;
output: out std_logic_vector(0 to 3);
end adder;
use work.myadder.all;
architecture struct of adder is
signal a: std_logic;
begin
u0: fulladder portmap(a1=>input1(0),a2=>input2(0),'0'=>c1,c2=>carryer,b=>output(0));
    a<=carryer;
u1: fulladder portmap(a1=>input1(1),a2=>input2(1),'0'=>c1,c2=>carryer,b=>output(1));
    a<=carryer;
u2: fulladder portmap(a1=>input1(2),a2=>input2(2),'0'=>c1,c2=>carryer,b=>output(2));
    a<=carryer;
u3: fulladder portmap(a1=>input1(3),a2=>input2(3),'0'=>c1,c2=>carryer,b=>output(3));
end struct;