testsuite.vhd

DAC converter design with Verilog code and testbench

----------------------------------------------------------------------------
----------------------------------------------------------------------------
--  The Free IP Project
--  VHDL Free-DAC Core Test Suite
--  (c) 2000, The Free IP Project and David Kessner
--
--
--  FREE IP GENERAL PUBLIC LICENSE
--  TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
--
--  1.  You may copy and distribute verbatim copies of this core, as long
--      as this file, and the other associated files, remain intact and
--      unmodified.  Modifications are outlined below.  
--  2.  You may use this core in any way, be it academic, commercial, or
--      military.  Modified or not.  
--  3.  Distribution of this core must be free of charge.  Charging is
--      allowed only for value added services.  Value added services
--      would include copying fees, modifications, customizations, and
--      inclusion in other products.
--  4.  If a modified source code is distributed, the original unmodified
--      source code must also be included (or a link to the Free IP web
--      site).  In the modified source code there must be clear
--      identification of the modified version.
--  5.  Visit the Free IP web site for additional information.
--      http://www.free-ip.com
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ncotest.all;
use work.free_dac_lib.all;
use work.conversions.all;


entity testsuite is
end testsuite;

architecture arch_testsuite of testsuite is
  signal clk		:std_logic := '1';
  signal reset		:std_logic := '1';
  signal sin		:std_logic_vector (15 downto 0) := (others=>'0');
  signal sin_unsigned	:std_logic_vector (15 downto 0) := (others=>'0');
  signal dac_out	:std_logic;
  signal pwm_out	:std_logic;

  constant sync		:std_logic := '0';
--constant freq		:std_logic_vector (15 downto 0) := "0000000000000001";  -- freq = 1 decimal = 1.526 KHz
  constant freq		:std_logic_vector (15 downto 0) := "0000000000001101";  -- freq = 13 decimal = 19.836 KHz

  type log_file is file of integer;
  file nco_log 		:log_file open write_mode is "dac_nco.log";
  file dac_log 		:log_file open write_mode is "dac_ds.log";
  file pwm_log 		:log_file open write_mode is "dac_pwm.log";

  signal count		:std_logic_vector (18 downto 0) := (others=>'0');
  
begin
  -- 100 MHz clock
  process (clk)
  begin
    if clk='1' then
      clk <= '0' after 5 ns, '1' after 10 ns;
    end if;
  end process;

  reset <= '1' after 0 ns, '0' after 51 ns;

  U1:  nco port map (reset, clk, sync, freq, sin);
  U2:  dac_ds
           generic map (n_bits => sin'high+1)
           port map (reset, clk, sin, dac_out);

  sin_unsigned <= sin + "1000000000000000";
  U3:  dac_pwm
           generic map (n_bits => sin_unsigned'high+1)
           port map (reset, clk, sin_unsigned, pwm_out);



  -- Count the samples
  process (reset, clk)
  begin
    if reset='1' then
      count <= (others=>'0');
    elsif clk'event and clk='1' then
      count <= count + 1;
    end if;
  end process;
  
  -- Output the waveform to the log file
  process (clk)
    variable a :integer :=0;
  begin
    if clk'event and clk='1' then
      if count = "1000000000010000000" then
	     assert 1=0
                    report "Simulation Ended Successfully, end of sample period."
                    severity failure;      
      
      elsif count>"0000000000001111111" then
        if dac_out='1' then
          a := 127;
        else
          a := -127;
        end if;

        write (dac_log, a);

        if pwm_out='1' then
          a := 127;
        else
          a := -127;
        end if;

        write (pwm_log, a);

        a := conv_integer(sin);
        write (nco_log, a);
      end if;
    end if;
  end process;
  
end arch_testsuite;