代码搜索:std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
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vhd conj.vhd
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-- Title : Conj.vhd
-- Project :
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www.eeworm.com/read/353880/10408811
vhd parallel.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/161339/10423615
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/161339/10423706
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/353706/10428942
vhd freqtest8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREQTEST8 IS
PORT (CLK1HZ : IN std_logic;
FSIN : IN std_logic;
DOUT : OUT std_logic_VECTOR(31 DOWNTO 0));
END FREQTEST8;
ARCHIT
www.eeworm.com/read/353706/10429318
vhd reg32b.vhd
LIBRARY IEEE; --32位锁存器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY REG32B IS
PORT ( LK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
www.eeworm.com/read/353705/10429417
vhd dvf.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DVF IS
PORT ( CLK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FOUT : OUT STD_LOG
www.eeworm.com/read/353703/10429691
vhd declcnt.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DECLCNT IS
PORT (CLK0,RST0,EN0 : IN STD_LOGIC;
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
www.eeworm.com/read/279503/10432051
vhdtst testbcd.vhdtst
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity TestBCD is
end TestBCD;
architecture Stimulus of TestBCD is
file RESULTS: text open
www.eeworm.com/read/279503/10432064
vhd utility.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package UTILITY IS
function fparity (vtctp : std_logic_vector) return std_logic;
end Utility;
library IEEE;
use IEEE.STD_LOGIC_1164.all;