declcnt.vhd

7段数码显示译码器设计7段数码是纯组合电路

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DECLCNT IS
 PORT (CLK0,RST0,EN0 : IN STD_LOGIC;
                LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
                COUT : OUT STD_LOGIC);
END;
ARCHITECTURE behav OF DECLCNT IS
  COMPONENT CNT16
    PORT (CLK,RST,EN : IN STD_LOGIC;
                  CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                COUT : OUT STD_LOGIC);
  END COMPONENT;
  COMPONENT DECL7S IS 
    PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)  ); 
  END COMPONENT;
SIGNAL B : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
L1 : CNT16 PORT MAP(CLK=>CLK0,RST=>RST0,EN=>EN0,CQ=>B,COUT=>COUT);
L2 : DECL7S PORT MAP(A=>B,LED7S=>LED7S);
END ARCHITECTURE behav;