reg32b.vhd

8位十六进制频率计设计 根据频率的定义和频率测量的基本原理

LIBRARY IEEE; --32位锁存器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY REG32B IS
    PORT (    LK : IN STD_LOGIC;
             DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
            DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END REG32B;
ARCHITECTURE behav OF REG32B IS
BEGIN
    PROCESS(LK,DIN)
   BEGIN
   IF LK'EVENT AND LK = '1' THEN DOUT <= DIN;
     END IF;
    END PROCESS;
END behav;