freqtest8.vhd

8位十六进制频率计设计 根据频率的定义和频率测量的基本原理

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREQTEST8 IS
PORT (CLK1HZ :  IN std_logic;
      FSIN  :  IN std_logic;
      DOUT :  OUT std_logic_VECTOR(31 DOWNTO 0));
END FREQTEST8;
ARCHITECTURE struc of FREQTEST8 IS
COMPONENT FTCTRL
   PORT(CLKK  :  IN   std_logic;
        CNT_EN :  OUT  std_logic;
        RST_CNT :  OUT  std_logic;
        Load     :  OUT  std_logic  );
END COMPONENT;
COMPONENT cnt10
   PORT (CLK,RST,EN  :  IN   std_logic;
                 CQ  :  OUT  std_logic_vector(3 downto 0);
              COUT  :  OUT  std_logic);
END COMPONENT;
COMPONENT REG32B
   PORT (LK  :  IN  std_logic;
        DIN  :  IN  std_logic_VECTOR(31 DOWNTO 0);
        DOUT :  OUT std_logic_VECTOR(31 DOWNTO 0));
END COMPONENT;
    SIGNAL  Load1 : std_logic;
    SIGNAL  CARRY_OUT1 : std_logic_VECTOR(6 DOWNTO 0);
    SIGNAL  CLR8: std_logic;
    SIGNAL  EN8: std_logic;
    SIGNAL  COUT0: std_logic;
    SIGNAL  COUT1: std_logic;
    SIGNAL  COUT2: std_logic;
    SIGNAL  COUT3: std_logic;
    SIGNAL  COUT4: std_logic;
    SIGNAL  COUT5: std_logic;
    SIGNAL  COUT6: std_logic;
    SIGNAL  CQ8  : std_logic_VECTOR(31 DOWNTO 0);
  BEGIN
L1:  cnt10 port map (CLK=>FSIN, RST=>CLR8, EN=>EN8, CQ=>CQ8(3 downto 0),COUT=>COUT0);
L2:  cnt10 port map (CLK=>COUT0, RST=>CLR8, EN=>EN8, CQ=>CQ8(7 downto 4),COUT=>COUT1);
L3:  cnt10 port map (CLK=>COUT1, RST=>CLR8, EN=>En8, CQ=>CQ8(11 downto 8),COUT=>COUT2);
L4:  cnt10 port map (CLK=>COUT2, RST=>CLR8, EN=>EN8, CQ=>CQ8(15 downto 12),COUT=>COUT3);
L5:  cnt10 port map (CLK=>COUT3, RST=>CLR8, EN=>EN8, CQ=>CQ8(19 downto 16),COUT=>COUT4);
L6:  cnt10 port map (CLK=>COUT4, RST=>CLR8, EN=>EN8, CQ=>CQ8(23 downto 20),COUT=>COUT5);
L7:  cnt10 port map (CLK=>COUT5, RST=>CLR8, EN=>EN8, CQ=>CQ8(27 downto 24),COUT=>COUT6);
L8:  cnt10 port map (CLK=>COUT6, RST=>CLR8, EN=>EN8, CQ=>CQ8(31 downto 28)); 
L9:  FTCTRL port map (CLKK=>CLK1HZ, CNT_EN=>EN8, RST_CNT=>CLR8, Load=>Load1);
L10:  REG32B port map (LK=>Load1, DIN=>CQ8, DOUT=>DOUT);
END struc;