代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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txt 移位寄存器.txt

-- -- --------------------------------------------------------------------------------------- -- DESCRIPTION : Shift register -- Type : univ -- Width : 4 --
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vhd shaomiaode.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY shaomiaode IS PORT( CP:IN STD_LOGIC; SEGOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SELOUT :OUT STD_LOGIC_V
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vhd zhonghe20.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY zhonghe20 IS PORT( CP,clr,zf,ff :IN STD_LOGIC; SEGOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SELOUT :OUT
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www.eeworm.com/read/166859/9993453

vhd shaomiao.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY shaomiao IS PORT( CP :IN STD_LOGIC; SEGOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SELOUT :OUT STD_LOGIC_V
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vhd zhonghe.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY zhonghe IS PORT( CP,clr,zf,ff :IN STD_LOGIC; SEGOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SELOUT :OUT STD
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vhd shaomiaod.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY shaomiaod IS PORT( CP :IN STD_LOGIC; SEGOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SELOUT :OUT STD_LOGIC_V
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vhd tansf.vhd

library ieee; use ieee.std_logic_1164.all; entity tansf is port(d1,d2,d3,d4 : in std_logic; q : out std_logic_vector(3 downto 0)); end tansf; architecture bb of tansf is begin process(d1,d2
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vhd selling.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY selling IS PORT( gw :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); dw :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); g1,d1,g2,d2
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vhd disp.vhd

library ieee; use ieee.std_logic_1164.all; entity disp is port( d:in std_logic_vector(3 downto 0); q:out std_logic_vector(6 downto 0) ); end disp; architecture b of disp is begin process
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www.eeworm.com/read/166859/9994018

vhd s4to1.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY s4to1 IS PORT( gw :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); dw :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); d1,d2,d3,d4 :
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