代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/374530/9400171
vhd sanjiao.vhd
--sanjiao 模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sanjiao is
port(
clk :in std_logic;
dout : out std_logic_vector(5 downto 0)
)
www.eeworm.com/read/374530/9400186
vhd updown2.vhd
-- updown2 模块(of testup_f_k)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity updown2 is
port(
r_in:in std_logic;
www.eeworm.com/read/374530/9400212
vhd decoder_3_8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder_3_8 is
port(a,b,c,e1,e2,e3:in std_logic;
y:out std_logic_vector(7
www.eeworm.com/read/374530/9400220
vhd rom256x8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY work;
USE work.ram_constants.ALL;
ENT
www.eeworm.com/read/374530/9400227
vhd decoder_4_16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder_4_16 is
port(a1,b1,c1,d1,g2a1,g2b1:in std_logic;
y1,y2:out std_logi
www.eeworm.com/read/177781/9432220
vhd andarith.vhd
library ieee;
use ieee.std_logic_1164.all;
entity andarith is
port(abin:in std_logic;
din:in std_logic_vector(7 downto 0);
dout:out std_logic_vector(7 downto 0));
end andarith;
ar
www.eeworm.com/read/177739/9433818
vhd decoder.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(clk: in std_logic;
data: in std_logic_vector(9 downto 0);
www.eeworm.com/read/177739/9433836
vhd lock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lock is
port(numh,numt,numo: in std_logic_vector(9 downto 0);
clk,change,tes
www.eeworm.com/read/177737/9433952
vhd decoder.vhd
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(sel:in std_logic_vector(2 downto 0);
clk:in std_logic;
en:in std_logic;
Y:out std_logic_vector(7 downto 0));
end
www.eeworm.com/read/177619/9443916
vhd bingzhuanchuan.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity bingzhuanchuan is
Port (cp:in std_logic;
cs:in std_logic;
datain:in s