lock.vhd

来自「这是使用VHDL语言编写的密码锁程序,供大家参考」· VHDL 代码 · 共 49 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lock is
port(numh,numt,numo: in std_logic_vector(9 downto 0);
     clk,change,test: in std_logic;
     displayh,displayt,displayo: out std_logic_vector(7 downto 0);
     lockopen,lockclose: out std_logic);
end entity;
architecture arch of lock is
component decoder is
port(clk: in std_logic;
     data: in std_logic_vector(9 downto 0);
     q0: out std_logic_vector(7 downto 0);
     q1: out std_logic_vector(3 downto 0));
end component;
signal enable0,enable1: std_logic;
signal temph,tempt,tempo: std_logic_vector(3 downto 0);
signal dech,dect,deco: std_logic_vector(3 downto 0);
begin
  enable0<=change and (not test);
  enable1<=test and (not change);
u0: decoder
    port map(clk=>clk,data=>numh,q0=>displayh,q1=>dech);
u1: decoder
    port map(clk=>clk,data=>numt,q0=>displayt,q1=>dect);
u2: decoder
    port map(clk=>clk,data=>numo,q0=>displayo,q1=>deco);
process(clk)
begin
  if clk'event and clk='1' then
    if enable0='1' then
        temph<=dech;
        tempt<=dect;
        tempo<=deco;
    end if;
    if enable1='1' then
      if temph=dech and tempt=dect and tempo=deco then
         lockopen<='1';
         lockclose<='0';
      else
         lockopen<='0';
         lockclose<='1';
      end if;
    end if;
  end if;
end process;
end arch;