decoder.vhd

来自「这是用VHDL编写的译码程序,程序简单易懂」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(sel:in std_logic_vector(2 downto 0);
     clk:in std_logic;
     en:in std_logic;
     Y:out std_logic_vector(7 downto 0));
end entity;
architecture rtl of decoder is
begin
 process (sel,clk,en)
 begin
 --Y<="11111111";
 if en='1'and rising_edge(clk) then
 case sel is
 --when "000"=>Y(0)<='0';
 --when "001"=>Y(1)<='0';
 --when "010"=>Y(2)<='0';
 --when "011"=>Y(3)<='0';
-- when "100"=>Y(4)<='0';
 --when "101"=>Y(5)<='0';
 --when "110"=>Y(6)<='0';
 --when "111"=>Y(7)<='0';
 when "000"=>Y<="11111110";
 when "001"=>Y<="11111101";
 when "010"=>Y<="11111011";
 when "011"=>Y<="11110111";
 when "100"=>Y<="11101111";
 when "101"=>Y<="11011111";
 when "110"=>Y<="10111111";
 when "111"=>Y<="01111111";
 when others =>Y<="11111111";
 end case;
 end if;
end process;
end rtl;