代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/248277/12586493

vhd division10.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity division10 is port(lin:in std_logic_vector(9 downto 0); clock:in std_logic;
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www.eeworm.com/read/248277/12586565

vhd bsr.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity bsr is port(din :in std_logic_vector(7 downto 0); s:in std_logic_vector(2 downto
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www.eeworm.com/read/147086/12589636

vhd fen30.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fen30 IS PORT( CP : IN STD_LOGIC; RESET : IN STD_LOGIC; OV
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www.eeworm.com/read/147086/12590011

vhd statmach.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY statmach IS PORT( CP : IN STD_LOGIC; RESET : IN STD_LOGIC; OV
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www.eeworm.com/read/334523/12595949

vhd hour1.vhd

Library ieee; --计时模块 Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity hour1 is Port(clkh,set,reset:in std_logic; h
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www.eeworm.com/read/334523/12595979

vhd minute1.vhd

Library ieee; --分钟模块 Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity minute1 is Port(clkm,set,reset:in std_logic;
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www.eeworm.com/read/334523/12596315

vhd month1.vhd

Library ieee; --月份模块 Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity month1 is Port(clkd,set,reset:in std_logic; mo1,mo
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www.eeworm.com/read/334523/12596363

vhd myclock.vhd

--顶层文件 Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity myclock is Port(clk,reset,set:in std_logic; en:in std_logic_ve
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www.eeworm.com/read/334523/12596463

vhd day1.vhd

Library ieee; --每月天数模块 Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity day1 is Port(clkday,set,reset:in std_logic; d1,d
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www.eeworm.com/read/334523/12596468

vhd second1.vhd

Library ieee; --秒钟模块 Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity second1 is Port(clk,set,reset:in std_logic;
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