statmach.vhd

工作原理： 脉冲输入

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY statmach IS
	PORT(
		CP		: IN	STD_LOGIC;
		RESET		: IN	STD_LOGIC;		
        OV     : OUT   STD_LOGIC;
        COUNT : OUT	STD_LOGIC_VECTOR(3 DOWNTO 0)
		);
END statmach;
ARCHITECTURE A OF statmach IS
	SIGNAL COUN :  STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CP)
   BEGIN
   IF RESET='1' THEN
           COUN<="0000";
           OV<='0';
   ELSIF (CP'EVENT AND CP='1') THEN
         COUN<=COUN+1;
         IF COUN="1001" THEN
         OV<='1';
          COUN<="0000";
         ELSE          
         OV<='0';
         END IF;
   END IF;
END PROCESS;
COUNT<=COUN;
END A;