代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/171518/9747626
vhd memoryremapper.vhd
--****************************************************************************************************
-- Memory remapper for ARM core simualtion
-- Designed by Ruslan Lepetenok
-- Modified 26.12.2
www.eeworm.com/read/171518/9747648
vhd abusmultiplexer.vhd
--****************************************************************************************************
-- A bus multiplexer for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 04.1
www.eeworm.com/read/171518/9747665
vhd msscomppackage.vhd
-- *****************************************************************************************
-- Components for ARM memory subsystem (simulation)
-- Designed by Ruslan Lepetenok
-- Modified 02.02.20
www.eeworm.com/read/171518/9747673
vhd mulctrlandregs.vhd
--****************************************************************************************************
-- Multiplier control and Partial Sum/Carry registers for ARM core
-- Designed by Ruslan Lepete
www.eeworm.com/read/171518/9747682
vhd multipliertestadder.vhd
--****************************************************************************************************
-- Adder for multiplier tester for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 27.01.
www.eeworm.com/read/171518/9747687
vhd arm7tdmis_top.vhd
--****************************************************************************************************
-- Top entity for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 12.02.2003
www.eeworm.com/read/171518/9747699
vhd multiplier.vhd
--****************************************************************************************************
-- Multiplier for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 12.02.2003
--*********
www.eeworm.com/read/171126/9769649
vhd top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
port( clk0 : in std_logic;--50MHz基准时钟信号;
www.eeworm.com/read/415944/11047241
vhd addbcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity addbcd is
port( -- data : in std_logic_vector(7 downto 0);
bcd1 : in std_logic_v
www.eeworm.com/read/270072/11049548
vhd cnt31.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt31 is
port(clk,en :in std_logic;
co:out std_logic;
q :buffer std_logic_vector(1 downto