代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/252132/12300642
vhd regne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;
E, Clock : IN
www.eeworm.com/read/252132/12300644
vhd shiftrne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- left-to-right shift register with parallel load and enable
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTO
www.eeworm.com/read/252132/12300653
vhd components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
-- 2-to-1 multiplexer
COMPONENT mux2to1
PORT ( w0, w1 : IN STD_LOGIC ;
s : IN STD_LOGIC ;
f : OUT STD_L
www.eeworm.com/read/252132/12300656
vhd shiftlne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- right-to-left shift register with parallel load and enable
ENTITY shiftlne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT( R : IN STD_LOGIC_VECTOR
www.eeworm.com/read/150153/12308907
vhd cnt8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt8 is
port(clk:in std_logic;
q:out std_logic_vector(2 downto 0));
end cnt8;
architecture behv of cnt8 is
www.eeworm.com/read/150153/12308948
vhd myreg.vhd
library ieee;
use ieee.std_logic_1164.all;
entity myreg is
port(data0:in std_logic_vector(3 downto 0);
data1:in std_logic_vector(3 downto 0);
data2:in std_logic_vector(3 downto 0);
dat
www.eeworm.com/read/150043/12322837
vhd serial_generatedinstance.vhd
--------------------------------------------------
-- Model : 8051 Behavioral Model,
-- VHDL Entity mc8051.serial.generatedInstance
--
-- Author : Michael Mayer (
www.eeworm.com/read/149999/12325860
vhd change.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity change is
port
( period,clk:in std_logic;
n1,n2,n3:in std_logic_vector(3 downto 0);
m1,m2,m3:in std_logi
www.eeworm.com/read/338024/12327951
vhd seri_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity seri_2 is
port (clk,start,x: in std_logic;
q: out std_logic_vector(1 downto
www.eeworm.com/read/338024/12328012
vhd select4_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity select4_1 is
port (en: in std_logic;
x_2: in std_logic_vector(1 downto 0)