seri_2.vhd

来自「用VHDL语言实现QPSK调制功能和解调功能,」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity seri_2 is
	port (clk,start,x: in std_logic;
		  q: out std_logic_vector(1 downto 0)
		   );
end seri_2;

architecture rel of seri_2 is
signal n:integer range 0 to 7;            --计数器
signal xx:std_logic_vector(1 downto 0):="ZZ";   --中间寄存器

 begin
	process(clk)
	begin
		if clk'event and clk='1' then 
          if start='0' then n<=0;    
          elsif n=0 then n<=1;q<=xx;xx(1)<=x;   
          elsif n=2 then n<=3;
          elsif n=4 then n<=5; xx(0)<=x;
          elsif n=6 then n<=7;
          else  n<=n+1;                         --串并转换
          end if;        
	    end if;
    end process;
end rel;