select4_1.vhd

来自「用VHDL语言实现QPSK调制功能和解调功能,」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity select4_1 is
	port (en: in std_logic;
	      x_2: in std_logic_vector(1 downto 0);
		  q: out std_logic_vector(7 downto 0)
		   );
end select4_1;

architecture rel of select4_1 is
 begin
	process(en)
	begin
		if (en'event and en='1') then
		    if x_2="00" then q<="00000000";

            elsif x_2="01" then q<="00011111";

            elsif x_2="10" then q<="00111111";
            else
                q<="01011111";  
           end if;       
	    end if;
    end process;
end rel;