cnt8.vhd

来自「福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd）」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt8 is
	port(clk:in	std_logic;
		 q:out	std_logic_vector(2 downto 0));
end cnt8;
architecture behv of cnt8 is
	signal temp: std_logic_vector(2 downto 0);
begin
	process(clk)
	begin
		if clk'event and clk='1' then
			if temp="111" then
				temp<="000";
			elsif temp="100" then temp<="110"; 
			elsif temp="001" then temp<="011"; 
			else
				temp<=temp+1;
			end if;
		end if;
	end process;
	q<=temp;
end behv;