代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/259243/11812372

vhd led1.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY LED IS PORT(CLK4HZ:IN STD_LOGIC; BUTTEN:IN STD_LOGIC; LED:OUT STD_L
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www.eeworm.com/read/259219/11814883

vhd 双口ram.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity dualram is generic (width : positive := 8; depth : po
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www.eeworm.com/read/345339/11819737

vhd lcd.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity lcd is Port ( clk : in std_logic; reset : in std_logic;
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www.eeworm.com/read/345339/11820236

vhd subcountor.vhd

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity subcountor is PORT( clk : IN STD_LOGIC; rst : IN STD_LOGIC; cont : OUT STD_LOGIC_VECTOR
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www.eeworm.com/read/345339/11820253

vhd cont.vhd

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cont is PORT( clk : IN STD_LOGIC; rst : IN STD_LOGIC; cont : OUT STD_LOGIC_VECTOR(3 DOW
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www.eeworm.com/read/156108/11827161

vhd cnt24.vhd

LIBRARY IEEE; -- 24进制计数器 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT24 IS PORT ( CLK,EN, U_D : IN STD_LOGIC;
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www.eeworm.com/read/344934/11851328

vhd qiangdaqi.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity qiangdaqi is port(clk : in std_logic; clk2: in std_logic; sel : in std_logic;
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www.eeworm.com/read/344934/11851340

bak qiangda.vhd.bak

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity qiangda is port(data : in std_logic_vector(7 downto 0); q: buffer std_logic_vector(3 downto 0);
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www.eeworm.com/read/344934/11851367

vhd qiangda.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity qiangda is port(data : in std_logic_vector(7 downto 0); q: buffer std_logic_vector(3 downto 0);
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www.eeworm.com/read/155467/11869537

vhd display.vhd

--Author : 屈峥 2002081212 --File Name : DISPLAY.vhd --Objective : 动态显示 -- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DISPLAY IS PORT (A1 : IN ST
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