cont.vhd

vhdl的很多例子

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cont is
 PORT( clk  :  IN  STD_LOGIC;
       rst  :  IN  STD_LOGIC;
       cont :  OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      full  :  OUT STD_LOGIC
 );
END cont;
ARCHITECTURE behav OF cont IS
  
  SIGNAL time   :  STD_LOGIC_VECTOR(3 DOWNTO 0);
  --SIGNAL full   :  STD_LOGIC;
  --SIGNAL ll,fclk :STD_LOGIC;
  
begin
  process(rst,clk)
begin
 if rst='1' then
   time<="1111";
  elsif rising_edge(clk) then
     if time=0 then 
       time<="1111";full<='1';
        else time <=time-1;full<='0';
      end if;
   end if;
end process;
cont<=time;

end behav;