双口ram.vhd

来自「07全国大学生电子设计竞赛C题获奖作品FPGA外围接口双口RAM部分源码」· VHDL 代码 · 共 55 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity dualram is

       generic
			(width : positive := 8;
             depth : positive := 12);
 
      port
       (------------------------- port a is only for writing -------------------------------
        clka :   in  std_logic;
        wr   :   in  std_logic;
        addra :  in  std_logic_vector(depth - 1 downto 0);
        datain : in  std_logic_vector(width - 1 downto 0);
        ------------------------------------------------------------------------------------
        ------------------------- port b is only for reading -------------------------------
        clkb :      in  std_logic;
        rd   :      in  std_logic;
        addrb :     in  std_logic_vector(depth - 1 downto 0);
        dataout :   out std_logic_vector(width - 1 downto 0)          
        ------------------------------------------------------------------------------------
       );
end entity dualram;

 
architecture Behavioral of dualram is

	type ram is array(2 ** depth - 1 downto 0) of std_logic_vector(width - 1 downto 0);
	signal  dualram :      ram;

begin

       process(clka, clkb)
       begin
              if clka'event and clka = '1' then
                     if wr = '0' then
                            dualram(conv_integer(addra)) <= datain;
                     end if;
              end if;
       end process;
   
       process(clkb)
       begin
              if clkb'event and clkb = '1' then
                     if rd = '0' then
                            dataout <= dualram(conv_integer(addrb));
                     end if;
              end if;
       end process;
end Behavioral;