📄 led1.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY LED IS
PORT(CLK4HZ:IN STD_LOGIC;
BUTTEN:IN STD_LOGIC;
LED:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY LED;
ARCHITECTURE ONE OF LED IS
SIGNAL B:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL C:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL SEL:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
BUTTEN_JISHU:PROCESS(BUTTEN)
BEGIN
IF FALLING_EDGE(BUTTEN) THEN
SEL<=SEL+1;
END IF;
END PROCESS BUTTEN_JISHU;
MAICHONG_JISHU:PROCESS(CLK4HZ)
BEGIN
IF RISING_EDGE(CLK4HZ) THEN
B<=B+1;C<=C+1;
IF C=5 THEN
C<="000";
END IF;
END IF;
END PROCESS MAICHONG_JISHU;
STYLE:PROCESS(B,C,SEL)
BEGIN
IF (SEL="00") THEN
CASE B IS
WHEN "00" => LED<="1110";
WHEN "01" => LED<="1101";
WHEN "10" => LED<="1011";
WHEN "11" => LED<="0111";
END CASE;
ELSIF (SEL="01") THEN
CASE B IS
WHEN "00" => LED<="0111";
WHEN "01" => LED<="1011";
WHEN "10" => LED<="1101";
WHEN "11" => LED<="1110";
END CASE;
ELSIF(SEL="10") THEN
CASE C IS
WHEN "000" => LED<="1110";
WHEN "001" => LED<="1101";
WHEN "010" => LED<="1011";
WHEN "011" => LED<="0111";
WHEN "100" => LED<="1011";
WHEN "101" => LED<="1101";
WHEN OTHERS =>NULL;
END CASE;
ELSIF (SEL="11") THEN
CASE C IS
WHEN "000" => LED<="0111";
WHEN "001" => LED<="0011";
WHEN "010" => LED<="0001";
WHEN "011" => LED<="0000";
WHEN "100" => LED<="0001";
WHEN "101" => LED<="0011";
WHEN OTHERS =>NULL;
END CASE;
END IF;
END PROCESS STYLE;
END ARCHITECTURE ONE;
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