代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/259758/11767520
vhd print3.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PRINT3 IS
PORT (RDY: BUFFER STD_LOGIC;
B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
TR, CLK, RESET: IN STD_LOGIC;
www.eeworm.com/read/259758/11768196
vhd print4.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PRINT4 IS
PORT (RDY: BUFFER STD_LOGIC;
B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
TR, CLK, RESET: IN STD_LOGIC;
www.eeworm.com/read/346092/11769383
vhd reg32bit.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg is
generic (n : natural := 32);
port (D : in std_logic_vector(31 downto 0);
Clock, Reset, Enable : in std_logic;
Q : out std_logic_vector(31 downt
www.eeworm.com/read/156773/11776186
vhd reg.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity reg is
port(reset,CS,A0,RD,WR:IN STD_LOGIC;
FE,PE,OVERFLOW,RBF,TBE:in STD_LOGIC;
IRQ:OUT STD_LOGIC;
www.eeworm.com/read/156773/11776195
vhd shifter.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity shifter is
port(A0:in std_logic;
RXD,LDRB,LDSR,RXEN,TBE:in std_logic;
RX_buf:out std_logic_vector(7 dow
www.eeworm.com/read/259614/11777919
txt ludeng.txt
目的和要求：
1．有mr(主红)、my（主黄）、mg（主绿）、cr（乡红）、cy（乡黄）、cg（乡绿）六盏交通灯需要控制；
2．交通灯由绿→红有4秒黄灯亮的间隔时间，由红→绿没有间隔时间；
3．系统有mrcy、mrcg、mycr、mgcr四个状态；
4．相间公路右侧各埋有一个传感器，当有车辆通过相间公路时，发出请求信号s；
5．平时系统停留在mgcr状态，一 ...
www.eeworm.com/read/345853/11786391
vhd ledcontrol.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ledcontrol IS
PORT(
reset,clk,urgen : IN STD_LOGIC;
state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
sub,s
www.eeworm.com/read/345853/11786530
vhd ledshow.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ledshow IS
PORT(
clk,urgen : IN STD_LOGIC;
state : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
sub,set1,set2
www.eeworm.com/read/156540/11793220
txt gwdvpb.txt
LIBRARY IEEE; -- 2003/7/21 GWDVPB
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY gwdvpb IS
PORT (CLK0 : IN STD_LOGIC; --CLOCK0 标准频率时钟信号
TCLK : IN STD_LOGI
www.eeworm.com/read/345690/11795153
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------