reg.vhd

本程序是用VHDL语言实现异步通信控制器

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity reg is
	port(reset,CS,A0,RD,WR:IN STD_LOGIC;
		 FE,PE,OVERFLOW,RBF,TBE:in STD_LOGIC;
			IRQ:OUT STD_LOGIC;
		 din:in std_logic_vector(7 downto 0);
		 status:out std_logic_vector(7 downto 0));
end;
architecture behavior of reg is
signal ERXE,ETBE,ERBF:STD_LOGIC;
begin
process(reset)
begin
	if(reset='1'and CS='0'and A0='1'and RD='1'and WR='0')then
		ERXE<=din(2);ETBE<=din(1);ERBF<=din(0);
	elsif(reset='0')then	ERXE<='0';ETBE<='0';ERBF<='0';
	end if;
end process;
status<="000"&FE&OVERFLOW&PE&TBE&RBF when CS='0'and A0='1'and RD='0'and WR='1';
IRQ<='1'WHEN(ERBF='1'AND RBF='1')OR(TBE='1'AND ETBE='1')OR(ERXE='1'AND(PE='1'OR OVERFLOW='1'OR PE='1'))
	ELSE '0';
end;