ludeng.txt

路灯的控制 还是不错的啊自己看看把

目的和要求：
   1．有mr(主红)、my（主黄）、mg（主绿）、cr（乡红）、cy（乡黄）、cg（乡绿）六盏交通灯需要控制；
   2．交通灯由绿→红有4秒黄灯亮的间隔时间，由红→绿没有间隔时间；
   3．系统有mrcy、mrcg、mycr、mgcr四个状态；
   4．相间公路右侧各埋有一个传感器，当有车辆通过相间公路时，发出请求信号s；
   5．平时系统停留在mgcr状态，一旦s信号有效，经mrcy转入mrcg状态，但要保证mrcg状态也不得短于一分钟；
   6．一旦s信号无效，系统脱离mrcg状态。随即经mrcy转入进入mgcr状态，计时s信号一直有效，mrcg状态也不得长于20秒钟。

实验仪器：gw/48系列eda开发系统(包含ep1k30tc144-3)；
编程环境：maxplus ii 10.2

vhdl程序： 分为三个底层文件和一个顶层文件：

1.控制模块――controlm.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity controlm is
  port (clk0,reset0,s0,c0  :in std_logic;
        ld0                :out std_logic;
        dinl0,dinh0        :out std_logic_vector(3 downto 0);
        state0             :out std_logic_vector(1 downto 0));
end controlm;
architecture behav of controlm is
  signal statenum:std_logic_vector(1 downto 0);
  signal ldt:std_logic;
  signal  reg:std_logic_vector(3 downto 0);
 begin
 state0<=statenum;
 ld0<=ldt;
 reg<=statenum&s0&c0;
 process(reg,clk0)
   begin
     if reset0='0' then
       statenum<="00";dinh0<="0101";dinl0<="1001";ldt<='0'; 
     elsif clk0'event and clk0='0' then        
        case reg is
          when "0100"|"0101"|"1101"|"1111"=> statenum<="00";dinh0<="0101";dinl0<="1001";ldt<='0';
          when "1000"|"1001"|"1011"       => statenum<="11";dinh0<="0000";dinl0<="0011";ldt<='0';
          when "0011"                     => statenum<="01";dinh0<="0000";dinl0<="0011";ldt<='0';
          when "0111"                     => statenum<="10";dinh0<="0001";dinl0<="1001";ldt<='0';
          when others                     => ldt<='1';
        end case;
     end if;
end process;
end behav;

2.计数模块－－mvc.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mvc is
  port(   cp1:in std_logic;
          ld1:in std_logic;
        dinl1:in std_logic_vector(3 downto 0);
        dinh1:in std_logic_vector(3 downto 0);
          ql1:out std_logic_vector(3 downto 0);
          qh1:out std_logic_vector(3 downto 0);
           c1:out std_logic);
end mvc;

architecture w of mvc is
signal qa,qat:std_logic_vector(3 downto 0);
signal qb,qbt:std_logic_vector(3 downto 0);
signal ca,cb :std_logic;

begin
  qh1<=qb;
  ql1<=qa;
  process(cp1)
  begin
    qat<=dinl1;
    if cp1'event and cp1='1' then
      if ld1='0' then qa<=qat;ca<='0';
      elsif(qa="0000" and qb="0000") then qa<="0000";
      elsif(qa="0000") then  qa<="1001";ca<='0';
      elsif(qa="0001") then ca<='1';qa<="0000";
      else qa<=qa-1;ca<='0';
      end if;
    end if;
  end process;

  process(ca,cp1)
  begin
    qbt<=dinh1;
    if cp1'event and cp1='1' then
      if ld1='0' then qb<=qbt;cb<='0';c1<='0';
      elsif(qb="0000" and qa="0000") then qb<="0000";
      elsif(qb="0000" and qa="0001") then c1<='1';
      elsif(ca='1')                  then  qb<=qb-1;
      end if;
    end if;
  end process;
end w;

3.信号转换模块――tolight.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tolight is
  port (     clk2:in std_logic;
        statenum2:in std_logic_vector(1 downto 0);
        mr2,my2,mg2,cr2,cy2,cg2:out std_logic);
end tolight;
architecture behav of tolight is
begin
  process(clk2)
    begin
      if clk2'event and clk2='1' then
        case statenum2(1 downto 0) is
          when   "00"=>mr2<='0';my2<='0';mg2<='1';cr2<='1';cy2<='0';cg2<='0';
          when   "01"=>mr2<='0';my2<='1';mg2<='0';cr2<='1';cy2<='0';cg2<='0';
          when   "10"=>mr2<='1';my2<='0';mg2<='0';cr2<='0';cy2<='0';cg2<='1'; 
          when   "11"=>mr2<='1';my2<='0';mg2<='0';cr2<='0';cy2<='1';cg2<='0';
          when others=>mr2<='0';my2<='0';mg2<='1';cr2<='1';cy2<='0';cg2<='0';
        end case;
      end if;
  end process;
end behav;

4.顶层文件――traffic.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity traffic is
  port(   clk:in std_logic;
          s  :in std_logic;
        reset:in std_logic;
        mr,my,mg,cr,cy,cg:out std_logic;
         time:out std_logic_vector(7 downto 0));
end traffic;
architecture behav of traffic is
component controlm is
  port (clk0,reset0,s0,c0  :in std_logic;
        ld0            :out std_logic;
        dinl0,dinh0    :out std_logic_vector(3 downto 0);
        state0         :out std_logic_vector(1 downto 0));
end component controlm;
component mvc is
  port(   cp1:in  std_logic;
          ld1:in  std_logic;
        dinl1:in  std_logic_vector(3 downto 0);
        dinh1:in  std_logic_vector(3 downto 0);
          ql1:out std_logic_vector(3 downto 0);
          qh1:out std_logic_vector(3 downto 0);
           c1:out std_logic);
end component mvc;
component tolight is
  port (     clk2:in std_logic;
        statenum2:in std_logic_vector(1 downto 0);
        mr2,my2,mg2,cr2,cy2,cg2:out std_logic);
end component tolight;

signal c,ld     :std_logic;
signal dinl,dinh:std_logic_vector(3 downto 0);
signal statenum :std_logic_vector(1 downto 0);
begin
u1: controlm port map(clk0=>clk,reset0=>reset,s0=>s,c0=>c,ld0=>ld,dinl0=>dinl,dinh0=>dinh,state0=>statenum);
u2: mvc     port map(cp1=>clk,ld1=>ld,dinl1=>dinl,dinh1=>dinh,ql1=>time(3 downto 0),qh1=>time(7 downto 4),c1=>c);
u3: tolight port map(clk2=>clk,statenum2=>statenum,mr2=>mr,my2=>my,mg2=>mg,cr2=>cr,cy2=>cy,cg2=>cg);
end behav;

引脚锁定：
根据实验输入输出要求，选择模式五作为实验电路。
具体引脚锁定如下：
信号名 类型 使用电路信号 引脚
clk 输入 clock0 126
s 输入 键8 19
reset 输入 键7 18
mr 输出 d8 19
my 输出 d7 28
mg 输出 d6 27
cr 输出 d5 26
cy 输出 d4 23
cg 输出 d3 22
time(7 downto 4) 输出 译码数码管8 96．95，92，91
time(3 downto 0) 输出 译码数码管7 90，89，88，87