代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/402018/11544071

vhd bsr.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity bsr is port(din :in std_logic_vector(7 downto 0); s:in std_logic_vector(2 downto
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www.eeworm.com/read/401197/11562547

vhd bl.vhd

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity bl is port ( BLCLK: in STD_LOGIC; reset :in std_logic;
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www.eeworm.com/read/401197/11562626

tdf changgel11.tdf

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity changedl is port ( ADDR: in STD_LOGIC_VECTOR (5 downto 0);
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www.eeworm.com/read/400990/11566315

vhd filter_liqiong.vhd

library IEEE; use IEEE.std_logic_1164.all; library xp2; use xp2.components.all; entity FILTER is Port ( rst : In std_logic; sdi : In std_logic;
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www.eeworm.com/read/400671/11570737

vhd my_pkg.vhd

library ieee; use ieee.std_logic_1164.all; package my_pkg is component div_clock port(clk: in std_logic; f50hz: out std_logic; f10hz: out std_logic;-- 5Hz output signal f5hz: out std_
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www.eeworm.com/read/400098/11583337

vhd counter24.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER24 IS PORT( CP : IN STD_LOGIC; BIN : OUT STD_LOGIC_VECTOR (5 DOWN
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www.eeworm.com/read/400018/11585800

txt bwcfq.txt

library ieee; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY part6 IS PORT(DATAA,DATAB:IN STD_LOGIC_VECTOR(7 DOWNTO 0); RESULT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END
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www.eeworm.com/read/400005/11586239

vhd dividend4.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity dividend4 is port(dividend_in:in std_logic_vector(7 downto 0); divisor:in std_lo
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www.eeworm.com/read/158727/11590157

vhd m4.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity m4 is port(clk :in std_logic; set :in std_logic; qin :in std_logic_vector(1 downto 0); q :buf
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www.eeworm.com/read/158727/11590166

vhd addm4.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity addm4 is port(clk :in std_logic; set :in std_logic; qin :in std_logic_vector(1 downto 0); q :
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