filter_liqiong.vhd

时钟滤波器设计

library IEEE;
use IEEE.std_logic_1164.all;
library xp2;
use xp2.components.all;

entity FILTER is
      Port (     rst : In    std_logic;
                 sdi : In    std_logic;
                fout : Out   std_logic;
                 sck : In    std_logic );

attribute LOC : string;
attribute LOC of rst	: signal is "157";
attribute LOC of sdi	: signal is "113";
attribute LOC of fout	: signal is "111";
attribute LOC of sck	: signal is "106";

end FILTER;

architecture SCHEMATIC of FILTER is

   SIGNAL gnd : std_logic := '0';
   SIGNAL vcc : std_logic := '1';

   signal     dina : std_logic_vector (7 downto 0);

   component REG_SHIFT8
      Port (     rst : In    std_logic;
                 SCK : In    std_logic;
                 SDI : In    std_logic;
                dout : Out   std_logic_vector (7 downto 0) );
   end component;

   component OUT_CTL
      Port (    dina : In    std_logic_vector (7 downto 0);
                 sck : In    std_logic;
               f_out : Out   std_logic );
   end component;

begin

   I1 : REG_SHIFT8
      Port Map ( rst=>rst, SCK=>sck, SDI=>sdi,
                 dout(7 downto 0)=>dina(7 downto 0) );
   I2 : OUT_CTL
      Port Map ( dina(7 downto 0)=>dina(7 downto 0), sck=>sck,
                 f_out=>fout );

end SCHEMATIC;