代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/301795/13848359
vhd result.vhd
-- output of CoreGen module generator
-- $Header: romrVHT.vhd,v 1.3 1998/06/15 16:22:02 tonyw Exp $
-- *****************************************************************
-- Copyright 1997-1998 - Xi
www.eeworm.com/read/301795/13848362
vhd radd16.vhd
-- output of CoreGen module generator
-- $Header: adreVHT.vhd,v 1.3 1998/06/15 17:52:34 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
www.eeworm.com/read/301795/13848375
vhd mux4w8.vhd
-- output of CoreGen module generator
-- $Header: mux4VHT.vhd,v 1.2 1998/06/15 17:58:03 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
www.eeworm.com/read/301795/13848397
vhd rsub16.vhd
-- output of CoreGen module generator
-- $Header: subreVHT.vhd,v 1.3 1998/06/15 17:53:11 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-1
www.eeworm.com/read/301598/13854256
vhd qiangdaqi.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity qiangdaqi is
Port ( clkin : in std_logic;
startin
www.eeworm.com/read/301598/13854269
vhd daoji10.vhd
--倒时时为30秒
--首先是10位倒计时
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity daoji10 is
Port ( EN,clk,rst : in std_logic;
www.eeworm.com/read/301494/13858268
vhd 加法器.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
www.eeworm.com/read/206369/13867076
txt vhdl-jishushizhong.txt
主程序：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity DLED is
port(
CLK1,CLK2: in STD_LOGIC;———————CLK1：时钟记数时钟，CLK2：扫描显示时钟
PUL
www.eeworm.com/read/115176/13867675
vhd v3mux1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity v3mux1 is port
(
clk :in std_logic;
decodein1,decodein2,decodein3 :in std_logic_vector(6 downto 0);
www.eeworm.com/read/301035/13868945
vhd dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC;
FWORD : IN S