vhdl-jishushizhong.txt

这是一个用VHDL编的一个计数时钟的设计,程序各个模块都有,希望和大家多多交流

主程序：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity DLED is
port(
CLK1,CLK2: in STD_LOGIC;———————CLK1：时钟记数时钟，CLK2：扫描显示时钟
PULSE1,PULSE2:in STD_LOGIC;————PULSE1：全部清零脉冲,PULSE2：秒钟清零脉冲
EDGE1,EDGE2:IN STD_LOGIC;——————EDGE1：小时调节脉冲,EDGE2分钟调节脉冲
RESET:IN STD_LOGIC;
K1:IN STD_LOGIC;—————————————————12|24小时制选择控键

LED_SA:OUT STD_LOGIC;
LED_SB:OUT STD_LOGIC;
LED_SC:OUT STD_LOGIC;——————————————扫描显示

LED_A:OUT STD_LOGIC;
LED_B:OUT STD_LOGIC;
LED_C:OUT STD_LOGIC;
LED_D:OUT STD_LOGIC;
LED_E:OUT STD_LOGIC;
LED_F:OUT STD_LOGIC;
LED_G:OUT STD_LOGIC;
LED_DP:OUT STD_LOGIC);——————————————数码管显示
END DLED;

ARCHITECTURE DLED_ARCH OF DLED IS
COMPONENT DLEDDIS————————————————时钟扫描显示模块
PORT(
HH:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
HL:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
MH:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ML:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SH:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SL:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CK:IN STD_LOGIC;
SEG:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;

COMPONENT S12_24——————————————————12|24小时制选择模块
PORT(
HH:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
HL:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SET12:IN STD_LOGIC;
ENT:IN STD_LOGIC;
RST:IN STD_LOGIC;
HRES:OUT STD_LOGIC
);
 END COMPONENT;

COMPONENT SENARY—————————————————时，分，秒高位记数模块
PORT(
RESET:IN STD_LOGIC;
CK:IN STD_LOGIC;
ENT:IN STD_LOGIC;
ENP:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
RCO:OUT STD_LOGIC
);
END COMPONENT;

COMPONENT DECIMAL————————————————时，分，秒低位记数模块
PORT(
RESET:IN STD_LOGIC;
CK:IN STD_LOGIC;
ENT:IN STD_LOGIC;
ENP:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
RCO:OUT STD_LOGIC
);
END COMPONENT;

SIGNAL HH:STD_LOGIC_VECTOR(3 DOWNTO 0); ————时高位信号
SIGNAL HL:STD_LOGIC_VECTOR(3 DOWNTO 0); ————时低位信号
SIGNAL MH:STD_LOGIC_VECTOR(3 DOWNTO 0); ————分高位信号
SIGNAL ML:STD_LOGIC_VECTOR(3 DOWNTO 0); ————分低信号
SIGNAL SH:STD_LOGIC_VECTOR(3 DOWNTO 0); ————秒高位信号
SIGNAL SL:STD_LOGIC_VECTOR(3 DOWNTO 0); ————秒低位信号
SIGNAL SEG:STD_LOGIC_VECTOR(6 DOWNTO 0); ————数码管显示信号
SIGNAL SEL:STD_LOGIC_VECTOR(2 DOWNTO 0); ————扫描显示信号

SIGNAL CK1HZ:STD_LOGIC;
SIGNAL RST:STD_LOGIC;

SIGNAL SRES:STD_LOGIC;
SIGNAL HRES:STD_LOGIC;
SIGNAL MLENT:STD_LOGIC;——————————————分钟工作信号
SIGNAL HLENT:STD_LOGIC;——————————————时钟工作信号

SIGNAL SHRCO :STD_LOGIC;
SIGNAL SLRCO:STD_LOGIC;
SIGNAL MHRCO:STD_LOGIC;
SIGNAL MLRCO:STD_LOGIC;
SIGNAL HHRCO:STD_LOGIC;
SIGNAL HLRCO:STD_LOGIC;

SIGNAL ENT:STD_LOGIC;
SIGNAL ENP:STD_LOGIC;
BEGIN

HH(3)<='0';—————————————————————确保时钟高位数字在0—2之间
MH(3)<='0'; ————————————————————确保分钟高位数字在0—5之间
SH(3)<='0'; ————————————————————确保秒钟高位数字在0—5之间

ENT<='1';
ENP<='1';

CK1HZ<=CLK1;

RST<=NOT PULSE1;
SRES<=RST OR PULSE2;
MLENT<=SHRCO OR EDGE2;—————————————给分钟工作信号赋值
HLENT<=MHRCO OR EDGE1; ————————————给时钟工作信号赋值

SECL:DECIMAL PORT MAP(SRES,CK1HZ,ENT,ENP,SL,SLRCO);
SECH:SENARY PORT MAP(SRES,CK1HZ,SLRCO,ENP,SH(2 DOWNTO 0),SHRCO);
MINL:DECIMAL PORT MAP(RST,CK1HZ,MLENT,ENP,ML,MLRCO);
MINH:SENARY PORT MAP(RST,CK1HZ,MLRCO,ENP,MH(2 DOWNTO 0),MHRCO);
HOURL:DECIMAL PORT MAP(HRES,CK1HZ,HLENT,ENP,HL,HLRCO);
HOURH:SENARY PORT MAP(HRES,CK1HZ,HLRCO,ENP,HH(2 DOWNTO 0),HHRCO);
DISPLAY:DLEDDIS PORT MAP(HH,HL,MH,ML,SH,SL,CLK2,SEG,SEL);
SEL12_24:S12_24 PORT MAP(HH,HL,K1,HLENT,RST,HRES);

————————————————————————以上8行程序生成本实验的原理图
LED_SA<=SEL(0);
LED_SB<=SEL(1);
LED_SC<=SEL(2);
————————————————————————以上三行程序实现扫描显示
LED_A<=SEG(0);
LED_B<=SEG(1);
LED_C<=SEG(2);
LED_D<=SEG(3);
LED_E<=SEG(4);
LED_F<=SEG(5);
LED_G<=SEG(6);
LED_DP<='0';
————————————————————————以上8行程序实现时钟的数字显示
END DLED_ARCH;

时钟扫描及显示程序：
LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DLEDDIS  IS
PORT(
HH    :IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
HL    :IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
MH    :IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
ML    :IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
SH    :IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
SL    :IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
CK    :IN  STD_LOGIC;————————————————扫描时钟
SEG    :OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);———时钟的数字显示信号
SEL    :OUT  STD_LOGIC_VECTOR(2 DOWNTO 0)———扫描检测信号
);
END DLEDDIS;
ARCHITECTURE DLEDDIS_ARCH OF DLEDDIS IS
SIGNAL NUM :STD_LOGIC_VECTOR(3 DOWNTO 0);——对应时钟显示的十进制数字信号
SIGNAL COUNT :STD_LOGIC_VECTOR(2 DOWNTO 0);—扫描信号
BEGIN 
 PROCESS (CK) ——————————————————扫描程序
BEGIN 
IF CK'EVENT AND CK='1'THEN————————————等待上升沿的到来
IF COUNT<5 THEN
    COUNT<=COUNT+1;
ELSE COUNT<="000"; 
END IF;
END IF;
END PROCESS; 
SEL<=COUNT;
NUM<=SL WHEN COUNT=0 ELSE
SH WHEN COUNT=1 ELSE
ML WHEN COUNT=2 ELSE
MH WHEN COUNT=3 ELSE
HL WHEN COUNT=4 ELSE
HH;———————————————————————————扫描时钟，分钟，秒钟各位
SEG<="0111111"WHEN NUM=0 ELSE
	"0000110"WHEN NUM=1 ELSE
	"1011011"WHEN NUM=2 ELSE
	"1001111"WHEN NUM=3 ELSE
	"1100110"WHEN NUM=4 ELSE
	"1101101"WHEN NUM=5 ELSE
	"1111101"WHEN NUM=6 ELSE
	"0000111"WHEN NUM=7 ELSE
	"1111111"WHEN NUM=8 ELSE
	"1101111"WHEN NUM=9 ELSE
	"1110111"WHEN NUM=10 ELSE
	"1111100"WHEN NUM=11 ELSE
	"0111001"WHEN NUM=12 ELSE
	"1011110"WHEN NUM=13 ELSE
	"1111001"WHEN NUM=14 ELSE
	"1110001"WHEN NUM=15 ELSE
	"0000000";———————————————————————时钟数字显示
END DLEDDIS_ARCH;

12|24小时制转换程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY S12_24 IS
PORT(
HH     :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
HL     :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SET12  :IN STD_LOGIC;——————————————————12|24小时制选择端口
ENT    :IN STD_LOGIC;
RST    :IN STD_LOGIC;——————————————————小时位清零端口
HRES  :OUT STD_LOGIC
     );
END S12_24;
ARCHITECTURE S12_24_ARCH OF S12_24 IS 
SIGNAL NUM   :STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN 
NUM<=HH(1 DOWNTO 0)& HL;
HRES<=NOT SET12    WHEN NUM="100100"ELSE——————选择24小时制
         SET12   WHEN NUM ="010010"ELSE————————选择12小时制
         '1'      WHEN RST ='1' ELSE————————————小时位清零
         '0';————————————————————————小时位正常工作
END S12_24_ARCH;

时、分、秒高位记数程序library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY SENARY IS
PORT(
      RESET: IN STD_LOGIC;
       CK:   IN STD_LOGIC;
 ENT: IN STD_LOGIC;
 ENP: IN STD_LOGIC;
 Q:OUT   STD_LOGIC_VECTOR(2DOWNTO 0);
 RCO:     OUT STD_LOGIC————————————————向前记数端口
  );
END SENARY;

architecture SENARY_ARCH OF SENARY IS
SIGNAL D  : STD_LOGIC_VECTOR(2DOWNTO 0);
BEGIN
PROCESS(RESET,CK,ENT,ENP)
BEGIN
  IF RESET='1'THEN
 D<="000";————————————————————————记数器清零
ELSIF CK'event AND CK='1'THEN
IF ENP='1' AND ENT='1'THEN
IF D<5 THEN
  D<=D+1;
ELSE D<="000";
END IF;
END IF;
END IF;————————————————————————进行六进制记数
IF D=5 AND ENT='1'THEN
 RCO<='1';———————————————————————继续向前记数
ELSE RCO<='0';
END IF;
END PROCESS;
Q<=D;
END SENARY_ARCH;

时、分、秒低位记数程序：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DECIMAL IS
PORT(
RESET:IN STD_LOGIC;
CK:IN STD_LOGIC;
ENT:IN STD_LOGIC;
ENP:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
RCO:OUT STD_LOGIC——————————————————向前记数端口
);
END DECIMAL;
ARCHITECTURE DECIMAL_ARCH OF DECIMAL IS
SIGNAL D:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(RESET,CK,ENT,ENP)
BEGIN
IF RESET='1'
THEN D<="0000";————————————————————记数器清零
ELSIF CK'EVENT AND CK='1' THEN
IF ENP='1' AND ENT='1' THEN
IF D<9 THEN
D<=D+1;
ELSE D<="0000";
END IF;
END IF;
END IF;————————————————————————进行十进制记数
IF D=9 AND ENT ='1' THEN
RCO<='1';———————————————————————继续向前记数
ELSE RCO<='0';
END IF;
END PROCESS;
Q<=D;
END DECIMAL_ARCH;