qiangdaqi.vhd

实现抢答器功能

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity qiangdaqi is
    Port ( clkin : in std_logic;                 
           startin : in std_logic;                
           sin:in std_logic_vector(6 downto 0);
           dt,sh,sl: out std_logic_vector(3 downto 0));
end qiangdaqi;

architecture Behavioral of qiangdaqi is
   	signal c1,c2,c3:std_logic;
	
 component daoji10 is
             Port ( EN,clk,rst : in std_logic;
                    CQ : out std_logic_vector(3 downto 0);
                     CL : out std_logic);
              end component daoji10;

	  component  daoji3 is
             Port ( EN,clk,rst : in std_logic;
                    CQ : out std_logic_vector(3 downto 0);
                    CL : out std_logic);
          end component daoji3;

	  

          component qiangda is 
             port(clk:in std_logic;
                  suocuns:in std_logic;
                  s:in std_logic_vector(6 downto 0);
                  start:in std_logic;
                  data: out std_logic_vector(3 downto 0);
                  successful:out std_logic);
           end component qiangda;
begin 
u1: qiangda port map( clk=>clkin,start=>startin,	           
			                 s=>sin,
                              suocuns=>c1,
			                    data=>dt,
                              successful=>c2);
u2: daoji10 port map( clk=>clkin,rst=>startin,en=>c2,	           
			              cq=>sl,
			               cl=>c3);
u3: daoji3 port map( clk=>c3,rst=>startin,en=>c2,	         
			               CQ=>sh,
			               cL=>c1);

end Behavioral;