代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/304223/13798140

vhd wogodiv.vhd

--成功作品；以后总结 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY wogodiv IS PORT( CLK:IN STD_LOGIC; outclk:out std_logic); end wogodiv; ARCHITECTURE meter OF wogodiv
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www.eeworm.com/read/304223/13798156

vhd counter10.vhd

--文件名：counter10.vhd。 --功能：10进制计数器，有进位C --最后修改日期： library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter10 is Port ( clk :
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www.eeworm.com/read/304223/13798251

vhd counter24.vhd

--文件名：counter24.vhd。 --功能：24进制计数器。 --最后修改日期：2008.04.26 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter24 is Port (
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www.eeworm.com/read/304052/13802403

vhd ps7.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ps7 is port(clk:in std_logic; load:in std_logic; q:out std_logic; count1:out std_logic_vector(7 downto 0) );
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www.eeworm.com/read/304049/13803359

vhd ps7.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ps7 is port(clk:in std_logic; load:in std_logic; q:out std_logic; count1:out std_logic_vector(8 downto 0) );
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www.eeworm.com/read/302931/13824732

vhd nia.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity nia is port (clk, ena: in std_logic; dn, qn: out std_logic_vector(3 downto 0); yf: out std_
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www.eeworm.com/read/302408/13836103

vhd v1.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity v1 is port(cp,intr:in std_logic; da:in std_logic_vector(7 downto 0); -- ad:out std_logic_vector(7
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www.eeworm.com/read/302408/13836124

vhd v.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity v is port(cp,intr:in std_logic; da:in std_logic_vector(7 downto 0); -- ad:out std_logic_vector(7
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www.eeworm.com/read/302408/13836148

vhd c_1000.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity c_1000 is port(clk:in std_logic; co:out std_logic); end c_1000; architecture rtl of c_1000 is
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www.eeworm.com/read/302403/13836338

vhd vgacore..vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vgacore is Port ( clk : in std_logic; reset : in std_logic;
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